How to time inputs into a circuit

Question

Say i have a controller circuit which has a clock frequency of 100Hz, there are input signals eds,enable,reset which will come from other circuits or a computer, how do i time these inputs to stabilize just before the rising edge of the 100Hz clock in controller circuit?

My thoughts are maybe to use a memory device like registers to store data from external circuit at a different clock frequency to controller circuit, then read the data using a clock frequency with a rising edge just before the rising edge of the controller 100hz clock?

Ive also head FIFO can be used to connect 2 circuits with different clock frequencies, is this any useful?

Answer 1

The issue you describe is called Metastability and is usually addressed by using input flipflops. This means before using your signal in any logic, sample it in a process like

 synch_process : PROCESS(rst_i, clk_i)
 BEGIN
    IF rst_i = '1' THEN
        internal_reg  <= '0';
    ELSIF rising_edge(clk_i) THEN
        internal_reg  <= external_sig;
    END IF;
END PROCESS synch_process;

where external_sig is the signal from the input pin. With the process you reduce the chance of Metastability.

As stated by The Photon already, this is caused by a violation of the setup or hold time of the chips input. As these are getting shorter with newer chips, they problem gets less dramatic, but it's still good practise to feed them at least through one flipflop.

Answer 2

You need at least two flip-flops to synchronise the signal to the clock. One flip-flop is not reliable.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Sync is
    generic
    (
        SYNC_BITS: positive := 3  -- Number of bits in the synchronisation buffer (2 minimum).
    );
    port
    (
        clock : in std_logic;
        input : in std_logic;  -- Asynchronous input.
        output: out std_logic  -- Synchronous output.
    );
end entity;

architecture V1 of Sync is

    constant SYNC_BUFFER_MSB: positive := SYNC_BITS - 1;
    signal sync_buffer: std_logic_vector(SYNC_BUFFER_MSB downto 0) := (others => '0');  -- N-bit synchronisation buffer (2 bits minimum).
    alias sync_input: std_logic is sync_buffer(SYNC_BUFFER_MSB);  -- The synchronised input is the MSB of the synchronisation buffer.

begin

    assert SYNC_BITS >= 2 report "Need a minimum of 2 bits in the synchronisation buffer.";

    process(clock)
    begin
        if rising_edge(clock) then
            sync_buffer <= sync_buffer(SYNC_BUFFER_MSB - 1 downto 0) & input;
        end if;
        output <= sync_input;
    end process;

end architecture;

Metastability

Figures from Digital Design and Computer Architecture by Harris & Harris

Figure 1 – Input changing before, after or during aperture.

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Figure 2 – Simple synchroniser.

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If the input, D, changes within the aperture (set-up and hold time) around the clock edge, the output, D2, is undetermined (metastable) and will take time to resolve to logic 0 or logic 1.

If the resolution time is less than the clock period minus the set-up time, the input to the second flip-flop will be stable, thus the output will successfully follow the input on the next clock edge.

If the resolution time is greater than the clock period minus the set-up time, the input to the second flip-flop will be between 0 and 1 (metastable) on the clock edge causing, it too, to become metastable:

\$ t_{resolution} > T_{clock} - t_{setup} \$

...so, three flip-flops are needed.

With higher clock frequencies, the ratio of resolution time, \$t_{resolution}\$, to clock period, \$T_{clock}\$, increases, necessitating even more flip-flops to satisfy the following equations:

\$ t_{resolution} < N_{cycles} \times T_{clock} - t_{setup} \$

\$ N_{flipflops} = N_{cycles} + 1 \$

...where \$N_{cycles} >= 1\$ and is the number of clock cycles to wait for resolution, thus giving a minimum of two flip-flops in the synchronisation buffer/chain.

Answer 3

There's no reason to stabilize the inputs just before the clock edge. As long as they meet setup and hold requirements, it doesn't matter how long before the edge they become stable.

If you want a design with margin, the longer they are stable before the edge, the better. But of course, the longer they are stable after the previous edge, the better for the timing margin on that edge. That leads us to generally try to get our inputs to transition ~1/2 cycle before the clock edge if we can.

My thoughts are maybe to use a memory device like registers to store data from external circuit at a different clock frequency to controller circuit, then read the data using a clock frequency with a rising edge just before the rising edge of the controller 100hz clock? ... Ive also head FIFO can be used to connect 2 circuits with different clock frequencies, is this any useful?

How is your idea (registers that store data according to one clock, and then reading it with a different clock) different from a FIFO?