I'm trying to design an asynchronous counter with JK flip- flops, with an arbitrary sequence.

enter image description here

The sequence is: 0, 1, 2, 3, 4, 5, 2 ?

I know how to solve this kind of problems, but in this case how can one solve this problem with the 6 and 7 ? Because a state can only have one next state ?

Edit: This is what I did so far after doing the K maps. I get J2 = 0, K2 = Q1, J1 = 0, K1 = 0, J0 = 0, K0 = Q2Q1. But when I try to simulate it in multisim, it gets stuck to 0. Did I make a mistake in my k map simplifications or is there an issue my circuit ?

N.B. in this image, Q1 is the LSB, Q2 is the '2' bit, Q3 is '4'

  • \$\begingroup\$ is this a school assignment? .... how does it get to state 6 or state 7 ? \$\endgroup\$ – jsotola Apr 7 '18 at 20:25
  • \$\begingroup\$ yes, i have no idea how it can get to the state 6 or 7... \$\endgroup\$ – Ahhh Physics Apr 7 '18 at 20:50
  • \$\begingroup\$ Then you also have no idea how it can get to 0. \$\endgroup\$ – Chris Stratton Apr 8 '18 at 0:42
  • \$\begingroup\$ Use a PROM to control the state machine. \$\endgroup\$ – analogsystemsrf Apr 8 '18 at 4:27
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    \$\begingroup\$ Voting to close as the problem behind this question simple isn't answerable until you have a complete specification. With what you have right now there are many approaches that could be taken, but each would rely on unvalidated assumptions as to what behavior is actually desired. Don't guess or ask us to - re-read the requirement, have a discussion with the stakeholders, or examine the application to more carefully determine the need. \$\endgroup\$ – Chris Stratton Apr 8 '18 at 17:54

Design the state transitions for 6 and 7 as well (next state = anything but 6 or 7. 2 is OK.) Otherwise a glitch may cause your counter to lock up in an undefined state. Use the "else" case if your design environment allows it.


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