I read that FinFET transistors were introduced to avoid the problems due to downscaling of MOSFET size, ie reduce the Short Channel Effects (SCEs) like DIBL, Hot Electron effects etc.
But how does the FinFET overcome these problems?
Or am I wrong? Is FinFET released to overcome any other problems in present planar MOSFETs?
finFETs are new generation transistors which utilize tri-gate structure. In contrast to planar transistors where the Gate electrode was (usually) above the channel, the Gate electrode "wraps" the channel from three sides in finFETs:
The immediate and obvious advantage of finFETs is that the effective width of the channel becomes:
$$W_{eff}=2H_{Si}+W_{Si}$$
The above dependence is revolutionary in that the current capability of the transistor (which is lineaw in \$W_{eff}\$) may be increased by employing the "vertical dimension" - the transistor's height affects its current capability. However, it is not that simple to increase the height of the fins - there are many physical issues which must be addressed.
There are basically two major technologies for finFETs manufacturing: Silicon-on-Insulator (SOI) finFETs and Bulk finFETs:
The very first finFETs were manufactured on top of insulating layer. The fact that the current can't flow "underneath" the gate when the transistor is in OFF state reduces the leakage current. Alternative techniques for stopping leakage current from flowing in the bulk were introduced later, which allowed for manufacturing of Bulk finFETs. This technique utilizes very high doping gradients along the height of the fin in order to prevent the current from flowing in the bulk.
It is true that finFETs allow for reducing of DIBL effect due to intrinsically higher level of Gate control over the channel. This control comes from the fact that may depletion regions are bounded by the fin itself and do not extend into the bulk. However DIBL is still one of the major factors which affects finFETs threshold voltages. The following graph shows the profiles of constant DIBL on height ratio vs. width ratio graph:
One of the advantages of Bulk finFETs is apparent from the above graph: constrained by the same DIBL level, higher doping Bulk finFETs allow for physically higher fins (higher \$W_{eff}\$) as compared to SOI ones.
The fact that there is tight connection between \$W_{eff}\$ and \$L_D\$ is not special for finFETs - all deep submicron planar technologies also suffer from narrow width effects.
This was the basic overview of finFETs. I'm not that into their physics for more elaborate explanations.
As for finFETs adoption: Intel has already adopted finFETs (if I'm not mistaken, starting with 22nm technology). TSMC and Global Foundries are going to introduce their finFET processes in a few months (or, maybe, they have already introduced them).
FinFETs are based on a polysilicon gate which wraps around the source/drain and body areas ( diffusion ) of the transistor. In that way, you can deplete the channel fully because the electric field permeates in 3 directions (top and both sides) rather than just from the top as in a planar gate.
When you can fully deplete the channel, the need for doping in the silicon decreases or is eliminated. This lowers cost for manufacture on the channel doping step. Also, when you don't have to dope as heavily you increase matching between transistors which means more stable Vt and better gate-channel modulation. Another side effect of a fully depleted body is lowered gate leakage, so lowered quiescent power in the VLSI implementation -- but the physics behind this benefit are unclear to me.
