Sensitivity list for clock edge and state change

Question

Not sure if this is correct implementation, although it works so far. I output the data on the rising edge of the FETCH signal (this is not a clock). The data should only be out in the OUTP state. This also counts how many words were output so far, and the state machine (not shown) transitions to a different state if the word count reaches some value.

always @(posedge FETCH)
    case(state)
        OUTP:   begin
                OUT_DATA <= DATA[WordCounter];
                WordCounter <= WordCounter + 1 ;
                end
        default:WordCounter <= 6'd0;
    endcase

The problem is that to reset the WordCounter, I must pulse FETCH signal when not in the OUTP state. Is there a better way to rewrite this code, so I can fetch the data on the edge, but the WordCounter can be reset in any state other than OUTP not requiring a rising edge?

Answer 1

I output the data on the rising edge of the FETCH signal (this is not a clock).

You change OUT_DATA and WordCounter on the rising edge of FETCH (but not merely to reset or preset them). Therefore FETCH is a clock (at least for this subcircuit).

If you don't want to use FETCH as a clock, but still watch its rising edges, you need to have another clock signal to use, and it must be guaranteed to have at least one rising edge for each pulse of FETCH. Then you can do

reg FETCH2;
always @(posedge CLK) begin
    FETCH2 <= FETCH;
    if ( state == OUTP ) begin
        if (FETCH & ~FETCH2) begin // rising edge of FETCH
            OUT_DATA <= DATA[WordCounter];
            WordCounter <= WordCounter + 1;
        end
    end
    else begin
        WordCounter <= 0;
    end
end

Answer 2

Strictly answering the question this code gives you a separate signal which will reset the variables:

always @(posedge FETCH or posedge clear)
begin
   if (clear)
   begin 
      OUT_DATA  <= out_data_reset_value;
      WordCounter  <= WordCounter _reset_value;
   end
   else
      case(state)
          OUTP:   begin
                  OUT_DATA <= DATA[WordCounter];
                  WordCounter <= WordCounter + 1 ;
                  end
          default:WordCounter <= 6'd0;
      endcase
end

But, as my text "Strictly ..." already suggests, that coding style is very much frowned upon. You should always try to make all your code synchronous to one clock and not introduce other 'clocks'. (Which FETCH is). Using my code with an asynchronous clear introduces a whole new, extra set of potential race conditions. I personally would never use it. caveat emptor!!

In the mean time I see The_Photon is already elaborating on this.