# how do I implement a start timer in a digital circuit

In vhdl, I know how to code a start timer behavorially. However, if I have to implement such a counter to start based on a trigger, how could I implement such a counter?

My trigger is another signal that will be active for only one clock cycle. I'm breaking my head trying to think of how this is done. I could add logic to check if my trigger is active high (1 and-ed to my signal) but then it will go inactive after 1 clock cycle.

I've seen counters with enable but I want to count and stay counting no matter what.

• Your question is not clear, Do you want to have a hardware circuit or software solution ? Can you rephrase "I could add logic to check if my trigger is active high (1 and-ed to my signal) but then it will go inactive after 1 clock cycle."? – Damien Oct 8 '18 at 5:26
• @Damien Umm hardware but not HDL behavioral. I want to actually understand the circuit. But now that I think about it even more, Im realizing I'm not experimenting with Dff or other sequential logic modules enough. – Cit5 Oct 8 '18 at 6:09
• my trigger signal is from a circuit that checks if an event happens. but the event only happens once every so often. I want my counter to start only when the signal is active high. however, when it is active high, it will only be in that state for one clock cycle. so if I use that signal for my enable in my counter, my counter will stop after the first cycle is done. I also want to restart the counter again, once the trigger signal is active high again (which should be long after the counter ends). – Cit5 Oct 8 '18 at 6:12

You can also add a reset to the DFF if desired, to disable the enable and allow the circuit to be retrigger.
Assuming you're still talking about VHDL, to add a start signal just create a two state counter. One idle state where you're waiting for the enable signal to be active and then transit to the regular counter state.