drawing a circuit, nand gates

Task: Construct an AND circuit with 8 inputs, a circuit which implements the expression a∧b∧c∧d∧e∧f∧g∧h.

Condition: Use only NAND-Gates with two inputs to solve this task.

Could anyone explain to me how to solve this question?

Thanks.

Edit: My thought would be to do sth. like this:

https://crcit.net/c/df53a1d9

Could that be right?

Edit: My new idea:

simulate this circuit – Schematic created using CircuitLab

• Welcome to EE.SE. Please upload the image into your question so that the question will make sense if the link dies and so that we don't have to all follow links just to understand what you are asking. There's an image upload button on the editor toolbar. – Transistor Apr 29 at 17:58
• Welcome to EE.SE! Please name all ports. Please use the built in schematic editor by pressing edit and click on the schematics symbol. – winny Apr 29 at 18:01
• Hint: two of your gates have their outputs tied together. What do you expect to happen if one is trying to output 1 and the other is trying to output 0? – The Photon Apr 29 at 18:02
• Did you test your idea? – Tony Stewart Sunnyskyguy EE75 Apr 29 at 18:05
• You will need 2x as many gates – Tony Stewart Sunnyskyguy EE75 Apr 29 at 18:12

Since you seem to be a bit lost. read https://en.wikipedia.org/wiki/De_Morgan's_laws#Engineering

let me show one way. Often we use X or Y or Z for outputs or f(ABCDEFGH)=...

$$\Y=((A\cdot B)\cdot (C\cdot D))\cdot ((E\cdot F)\cdot (G\cdot H))\$$

Since you must solve using 2in-NAND gates , I will use ! to indicate an inverted logic. (sometimes you will find ! used before or after brackets, but you must be consistent!)

AND = $$\(A\cdot B)!! = (A\cdot B) \$$ with both inputs of a NAND gate joined to make it an inverter (INV).

$$\Y=(~~(A\cdot B)!!\cdot (C\cdot D)!!~~ )!!\cdot ((E\cdot F)!!\cdot (G\cdot H)!!)!!\$$

Cleaner notation removes the dot for AND but leaves + for OR.

$$\Y=~((AB~!!)(CD)!! ) ~ ((EF)!!(GH)!!)!!\$$

I should have labelled the inputs with ABC etc but I was too lazy.

Here is what it looks like with my simulator that denotes H,L for 1,0 where you can carefully click on any input ( without disconnecting it by dragging the mouse click ;)

So you see output is H only when all inputs are H.

• I think I understand it by time. How do you get the AND gates, which the arrow shows to? I just understand that the OR gate comes from not (abcd) which is according to DeMorgan's Theorem not (ab) + not (cd). Edit: Do you want to show with the AND gates that they are only inverted? – lightsodium May 3 at 18:54
• Yes inverting both inputs and outputs results in switching inputs NAND to OR which is not what you want. So do you understand that you must use De Morgan's Law to test your understanding is wrong and that the solution requires inverting each NAND ( due to restriction in question) – Tony Stewart Sunnyskyguy EE75 May 3 at 19:33
• I finally understood it! Thanks a lot. – lightsodium May 3 at 20:09
• so you now see the light of logic, now there are only a couple more rules, then methods to design it, good logic but for language there are 144 rules of bad logic defined by Aristotle and Plato. ha. ( called fallacies ) Language and Black's Law (for legal) still use these fundamental de Morgan's Laws for language – Tony Stewart Sunnyskyguy EE75 May 3 at 21:06

You want to write your expression using boolean algebra, then convert it (if necessary) using DeMorgan's theorem to a form that you can implement using NAND gates. For example, say you have A + B (A or B). This becomes:

A + B (starting equation) (A'B')' (DeMorgan's format)

You can easily implement (A'B')' using one NAND gate for the purpose of the inverted AND (as expected), and 2 more NAND gates as inverters for A and B.

Use this algorithm with any equation you have in order to get it in terms of NANDS, ANDs (NANDs plus one more NAND after it to invert it), or NOTs (use single NAND to invert)