It seems that a half adder (there are 2 inside a full adder) can't output both HIGH values for sum and carry, it's either Sum is 1 and Carry is 0 or the inverse. It's never Sum = 1 and Carry = 1.
To make it more explicit, the truth table of a half adder:
IN OUT A | B (or Cin) | S | C 0 | 0 | 0 | 0 0 | 1 | 1 | 0 1 | 0 | 1 | 0 1 | 1 | 0 | 1
The carry of the full adder is made with an OR gate, which can never receive 1 in both ins in this context. The difference between an OR and a XOR is that if both ins are HIGH the OR returns 1 and the XOR 0.
So an OR gate seems (at least to me, for now) to be inappropriate for that logic because it would act as if we were supposed to have that possibility, an OR gate outputs 1 if it receives both 1 in, right? Which a XOR gate wouldn't. I suppose it doesn't change anything as it's not supposed to happen so both components would work.
So why use an OR gate instead of a XOR? Is it because it's a less complex component? Is it some kind of convention? Or is it that if in any ("impossible") case both values are HIGH the output should be HIGH? (and possibly cause an error?)
Or did I miss something? I'm new to electronics and it bugged me...
edit: updated with image from @hacktastical and tried to clarify the question.