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I've been looking into some ICs now. Some of them have the calculated result (data) in twos complement form, placed in register to be read by other IC. What is the logic behind converting the data to twos complement form before its read?

Examples are as

  1. Analog to digital converter (Page 30 Output Data Format). LINK
  2. Digital Accelerometer (Page 1 General Description). LINK

I have seen similar behavior in CRC calculation for IEEE 802.3. For example if we calculate the 32-bit CRC (using x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 polynomial) the calculated CRC is bit reversed and complemented before transmission.

Well the question is why is it formatted in complement form? Can't it be read without the data being complemented?

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  • \$\begingroup\$ An example of a part that does the CRC the way you say would be helpful for answering that part of your question. \$\endgroup\$
    – The Photon
    Commented Nov 26, 2012 at 18:02
  • \$\begingroup\$ Your CRC example has nothing to do with the signed numbers some ADCs use. \$\endgroup\$
    – starblue
    Commented Nov 29, 2012 at 20:43

3 Answers 3

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For an ADC whose natural format is offset binary, 2's complement is the natural way to represent signed numbers. All it has to do is invert the MSB.

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    \$\begingroup\$ Agree that twos-complement is a natural format for data from devices that measure positive and negative values... but twos-complement involves more than a simple MSB inversion. \$\endgroup\$
    – B Pete
    Commented Nov 26, 2012 at 18:46
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    \$\begingroup\$ @BPete: No, it really is that simple. You're thinking of something else: How to convert a positive number into the corresponding negative number. \$\endgroup\$
    – Dave Tweed
    Commented Nov 26, 2012 at 19:02
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    \$\begingroup\$ @DaveTweed - Your're right, I was thinking about the negative to positive conversion to interpet the data... the conversion from offset binary to twos-comp (inside the ADC) is indeed an MSB inversion. \$\endgroup\$
    – B Pete
    Commented Nov 26, 2012 at 19:17
  • \$\begingroup\$ Another way to think about it is: To shift an 8-bit signed int range up into the unsigned range, you just have to add half the range, i.e. 0x80. This is equivalent to inverting the top bit. \$\endgroup\$
    – Rocketmagnet
    Commented Nov 27, 2012 at 15:14
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Most microcontrollers and microprocessors represent negative numbers in 2's complement form. And many ADCs are designed for use in very time-constrained real-time systems. Having a 2's complement format in an ADC (or other sensor) means that negative numbers are represented in a way your processor can use directly, without having to spend cycles doing the conversion from some other format.

In a CRC, I suspect the result is simply complemented (bitwise inverted, aka "1's complement"). A CRC is a purely integer calculation and doesn't involve negative numbers, so there's absolutely no sense to doing a 2's complement with that number. Why you would 1's complement it, I can't say, but it should make little difference to the user.

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The question comes down to how to represent negative numbers, since positive numbers are the same in most binary representations. For most cases, 2s complement is the most convenient way to represent negative numbers in binary. This is almost certainly how the processor that has to manipulate the A/D reading does its math, so presenting it in 2s complement directly in the A/D makes is easy for the processor.

Some A/Ds only measure positive voltages. Those can use unsigned binary. If you don't like 2s complement for negative values, what would you prefer? It seems most alternatives would cause more complication.

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