I am reading about the 10Gb/s Ethernet PHY for Altera FPGAs (datasheet here). I was impressed to know that, at the hardware level, the 10Gb/s is done serially.
Naively, I would think to do 10Gb/s serially, one needs a 10GHz clock. However, 10GHz seems awefully high for a clock, and the datasheet does not specify a 10GHz clock anywhere.
How is 10Gb/s serial communication done? What clocks drive such transfers?
On the Altera parts you provide some reference base clock like 156.25Mhz. Then the transceiver section has a PLL that brings the frequency up to I think half the rate. So it'll be 5 Ghz for for the 10Gb/s link. Or it might be lower if instead of having one 10Gb/s link you break it into 4 lanes like we do for the XAUI interface. That clock and the parallel data get fed into the serializer and out comes 10Gb/s serial data. That's the gist of it anyway. You can read more about how the Altera transceivers work here.
Here's an cut out from their documentation.
