I am working with an FPGA that does 10Gb ethernet. As I understand, at the PHY level the clock frequency is 322.265625 MHz for a 32 bit wide bus, but at the MAC level, the clock frequency is 156.25 MHz for a 64 bit wide bus. The diagram here shows the various frequencies.
The strange thing is that 156.25 * 2 is not equal to 322.265625.
How can the PHY and MAC operate at fundamentally different speeds? What is the advantage of changing clocks (especially that there are latency losses in the clock domain transition)? Will the PHY not receive data faster than it can output to the MAC?