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I am working with an FPGA that does 10Gb ethernet. As I understand, at the PHY level the clock frequency is 322.265625 MHz for a 32 bit wide bus, but at the MAC level, the clock frequency is 156.25 MHz for a 64 bit wide bus. The diagram here shows the various frequencies.

The strange thing is that 156.25 * 2 is not equal to 322.265625.

How can the PHY and MAC operate at fundamentally different speeds? What is the advantage of changing clocks (especially that there are latency losses in the clock domain transition)? Will the PHY not receive data faster than it can output to the MAC?

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10 Gb Ethernet uses a physical coding sublayer that puts 66 bits on the wire for every 64 bits of payload data.

The 322.265625 MHz reference clock is simply the aggregate wire bit rate (10.3125 GHz) divided by 32.

The payload clock rate of 156.25 MHz is simply the wire bit rate divided by 66.

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I'm not sure why you think the Altera 10GB MAC runs at "fundamentally different" speeds to the PHY. The Altera MAC is single clock domain. It runs on the recovered 156.25 Mhz clock output driven from the 10GB BaseR Phy Megacore.

The 10GB Base-R PHY has both a wire bit rate clock and the fabric speed post-serdes clocks, in the ratio explained by Dave.

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