Timing diagram and performance of Binary Counters

Question

I have a binary counter which is the following : https://www.onsemi.com/pdf/datasheet/mc14020b-d.pdf

I want to reset this counter with a signal. I want this signal to be the narrower, ie the length of the pulse to be minimum. But I have to verify that the narrower signal is still took into account by the counter. I imagine that the the length of the pulse cannot be as small as I want. There is a mention about "Reset pulse width" into the datasheet but I do not know if it is that data that I have to consider and if there are other parameters to consider. I do not want to take any risks

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Here is a better binary counters : https://www.mouser.fr/datasheet/2/308/1/MC74HC4020A_D-2315492.pdf

The reset pulse width is lower as the reset recovery time compared to the MC14020B but what is strange is that the maximum input rise time is very large ? What does "Maximum input Rise and Fall times" ? Does I have to consider that my pulse needs to be superior to the reset pulse width + the reset recovery time + the rise/fall time ?

Have a nice day :)

Answer 1

When speed matters, you won’t want to use 4xxx family high voltage logic and choose a family with a lower maximum Vdd.

The reasons for this is that newer, much smaller channels, have lower breakdown voltage, lower capacitance, lower RdsOn like 50 ohms for 74HCxx vs ~300 to 3k ohms for 4xxx family (18V to 3V) which on the CMOS drivers work fine but slower.

In your case you want to consider the largest pulse width, & recovery time and also derate for case temperatures above 25’C where they run slower due to higher RdsOn.