I am learning and experimenting on the 8051 (AT89C51). From what I have learnt so far regarding interrupts, I understand that an interrupt with a higher priority can interrupt an interrupt with a lower priority.
This could mean two things. Either it can mean that since the higher priority interrupt is checked first, if both the higher and lower priority interrupts activate at the same time, the higher priority will be serviced first, meaning, the higher priority interrupt will interrupt the lower priority interrupt preventing it's immediate execution until the higher priority interrupt is serviced.
Or, - for which i am posting this question mainly - it can mean that while a low priority interrupt is already being serviced, a higher priority interrupt can literally and actually interrupt it, make the MC jump to the higher priority interrupt's own service routine and after the higher priority interrupt is serviced, execution will return to where it jumped from in the interrupt service routine of the lower priority interrupt.
The second one seems the higher probability from what I am observing.
But this would imply a few things.
Firstly, if multiple interrupts are to be used, the program has to be designed carefully, otherwise it might be a mess. One interrupt can come up within a certain process of another interrupt, change register and other values, then the previous interrupt resumes and everything is messed up.
Secondly, as it seems naturally, the reset value of the IP (Interrupt Priority) register is 00000000b. That is, no interrupt is assigned an exceptional higher priority. And in this default stage, the priority organization is such:
INT0 (external interrupt 0) TF0 (timer interrupt 0) INT1 (external interrupt 1) TF1 (timer interrupt 1) serial communication
And as such, INT0 can interrupt TF0 while it is already being serviced, and TF0 can interrupt INT1 or TF1 while they are already being serviced, unless the priorities are altered in any manner.
Now my question specifically is, is my understanding regarding a higher priority interrupt interrupting a lower priority interrupt while it is already being serviced, correct?
And, is my (possible) conclusion regarding the default value of 0 of the IP register and the default higher priority interrupts interrupting the default lower priorities interrupts while they are already being serviced, unless the priorities are altered, correct?