Im trying to do a series of simple operations (multiplication, CA2, and, substraction) and then, based on the values of "sel", choose one of those possibilities, so essentially, a MUX, so far this is what I've got: .vhd :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practica_8_ejercicio_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
resultado : out STD_LOGIC_VECTOR (7 downto 0));
end practica_8_ejercicio_2;
architecture mul3x3 of practica_8_ejercicio_2 is
--signal resultadomul3x3 : STD_LOGIC_VECTOR (7 downto 0);
begin
resultado <= a * b;
end mul3x3;
architecture rest33 of practica_8_ejercicio_2 is
--signal resultadorest33 : STD_LOGIC_VECTOR (7 downto 0);
begin
resultado <= (a(3) & a(3)& a(3) & a(3) & a) - (b(3)& b(3) & b(3) & b(3) & b);
end rest33;
architecture aCA2 of practica_8_ejercicio_2 is
--signal resultadoaCA2 : STD_LOGIC_VECTOR (7 downto 0);
begin
resultado <= (not (a(3) & a(3) & a(3) & a(3) & a)) + "00000001";
end aCA2;
architecture aandb of practica_8_ejercicio_2 is
--signal resultadoand : STD_LOGIC_VECTOR (7 downto 0);
begin
resultado <= ("0000" & a) and ("0000" & b);
end aandb;
testbench:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity practica_8_ejercicio_2_TB is
-- Port ( );
end practica_8_ejercicio_2_TB;
architecture mul3x3 of practica_8_ejercicio_2_TB is
component practica_8_ejercicio_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
resultado : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal T_a: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_b: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_sel: STD_LOGIC_VECTOR (1 downto 0); --selector
signal T_resultado: STD_LOGIC_VECTOR (7 downto 0); -- salida
--signal T_resultadomul3x3 : STD_LOGIC_VECTOR (7 downto 0);
begin
-- INSTANCIACIÓN --
ETIQUETA: practica_8_ejercicio_2 port map (a => T_a,
b => T_b,
sel => T_sel,
resultado => T_resultado);
estimulos: process
begin
for I in 0 to 15 loop
T_a <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
T_b <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
wait for 1us;
end loop;
end process;
end mul3x3;
architecture rest33 of practica_8_ejercicio_2_TB is
component practica_8_ejercicio_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
resultado : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal T_a: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_b: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_sel: STD_LOGIC_VECTOR (1 downto 0); --selector
signal T_resultado: STD_LOGIC_VECTOR (7 downto 0); -- salida
--signal T_resultadorest33 : STD_LOGIC_VECTOR (7 downto 0);
begin
-- INSTANCIACIÓN --
ETIQUETA: practica_8_ejercicio_2 port map (a => T_a,
b => T_b,
sel => T_sel,
resultado => T_resultado);
estimulos: process
begin
T_sel <= "10";
for I in 0 to 15 loop
T_a <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
T_b <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
wait for 1us;
end loop;
end process;
end rest33;
architecture aCA2 of practica_8_ejercicio_2_TB is
component practica_8_ejercicio_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
resultado : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal T_a: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_b: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_sel: STD_LOGIC_VECTOR (1 downto 0); --selector
signal T_resultado: STD_LOGIC_VECTOR (7 downto 0); -- salida
--signal T_resultadoaCA2 : STD_LOGIC_VECTOR (7 downto 0);
begin
-- INSTANCIACIÓN --
ETIQUETA: practica_8_ejercicio_2 port map (a => T_a,
b => T_b,
sel => T_sel,
resultado => T_resultado);
estimulos: process
begin
T_sel <= "01";
for I in 0 to 15 loop
T_a <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
T_b <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
wait for 1us;
end loop;
end process;
end aCA2;
architecture aandb of practica_8_ejercicio_2_TB is
component practica_8_ejercicio_2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
resultado : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal T_a: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_b: STD_LOGIC_VECTOR (3 downto 0); -- entrada
signal T_sel: STD_LOGIC_VECTOR (1 downto 0); --selector
signal T_resultado: STD_LOGIC_VECTOR (7 downto 0); -- salida
--signal T_resultadoand : STD_LOGIC_VECTOR (7 downto 0);
begin
-- INSTANCIACIÓN --
ETIQUETA: practica_8_ejercicio_2 port map (a => T_a,
b => T_b,
sel => T_sel,
resultado => T_resultado);
estimulos: process
begin
T_sel <= "00";
for I in 0 to 15 loop
T_a <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
T_b <= STD_LOGIC_VECTOR (TO_UNSIGNED(I,4));
wait for 1us;
end loop;
end process;
end aandb;
Problem is, that it seems like the selector defaults to "00", meaning that the only that its taken into account is the 'a and b', in fact, when I run the simulations, 'sel' has a constant value of 00 and the only thing with red dots in the testbench and in the .vhd is the part with the and operation.
So how should I go about making the MUX out of these 4 different architectures ? I would need to create with the 4 possible values of 'sel', and in each case, assign to 'resultado' the output of each operation. but since each output is in a separate architecture, I dont know how I should do it. Forgot to mention, but those signals that are commented are the ones that I should use, but since they weren't doing anything for me at the moment, I commented them, but I'm supposed to have 1 signal for each output, and then I guess I should do something like this: resultado <= resultadomul3x3, but then again no idea how I should approach the situation with the MUX. Thanks in advance.
