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Is it possible to multiply the frequency of a digital signal using digital components alone, and at the same time, preserve the duty cycle?

I could finally come across the circuit below: it doubles the frequency by exploiting the propagation delays of the components, but sacrifices the duty cycle.

enter image description here

I was wondering if a better solution (that preserves duty cycle) exists, but could not find any. I know this can be done using PLL, but I'm looking for a solution which uses only digital components.

Thanks for your help

EDIT:

Sorry I didn't mention this earlier, but the input signal is the fastest one in the system. So, sampling it would not be possible.

EDIT 2:

A bit into the history behind this question: During the final year of my engineering degree (way back in 2009), we had this circuit-design contest in our college and I was part of the team that organized it. We wanted to make the event rather lively and after some brainstorming, we came up with this weird idea of a "frequency multiplier using only discrete logic gates" as one of the challenges. We were well aware that pure boolean logic could never achieve something like this, but then, real-world logic gates had propagation delays; so we quickly wired up the circuit above using 74xx gates and saw that it worked. So we gave it to the contestants, with a bonus offer for any team which preserved the duty cycle of the input wave. Even though many of them came up with the above circuit, no one was able to do the bonus part. So far I've not been successful in doing it myself; Google was not so helpful either.

So I was just wondering if someone in EE could help me out in case they've already had some experience on this. Even an answer which says "this can never be done" is welcome, though I have a gut feeling that there is some solution lying around..

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  • \$\begingroup\$ there is a frequency doubler configuration , you may find it on wiki. \$\endgroup\$ – Standard Sandun Feb 28 '13 at 18:55
  • \$\begingroup\$ What do you intend to do with the out signal? You're going to have a difficult time meeting timing on the rest of your chip if the 'clock' is not a known stable frequency. Also the frequency of your output signal will vary wildly from one piece of silicon to another, probably at least plus or minus 50% due to process variation. \$\endgroup\$ – Tim Feb 28 '13 at 19:13
  • \$\begingroup\$ Propagation delays are not digital. They are an analog artifact. Digital means we can describe this frequency doubler using boolean algebra and automata. \$\endgroup\$ – Kaz Mar 1 '13 at 5:01
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    \$\begingroup\$ If the input frequency is the highest one in the system, what kind of "multiplication" are we talking about? \$\endgroup\$ – Dave Tweed Mar 1 '13 at 5:09
  • \$\begingroup\$ @Kaz I completely agree. However, any real-world digital component would have a delay, so I guess we should rather treat delay as an integral part of a digital component. And I'm almost convinced that frequency multiplication can never be done without the aid of delays :) \$\endgroup\$ – nav Mar 1 '13 at 6:38
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Even a PLL isn't going to preserve the waveform (including duty cycle) of its reference input, unless you add a second circuit to it to specifically do that. For example, the PLL could drive a one-shot whose pulse width is controlled by a feedback loop that compares the output duty cycle with the input duty cycle.

The best way to do this in an all-digital manner is to have one circuit that measures the frequency and duty cycle of the input signal (if those are the only two parameters you care about), and have another circuit that synthesizes a new signal with the same duty cycle and the desired frequency based on those measured values. (I have done something like this myself when building FPGAs that need to do frame rate doubling/halving on video signals.)

The output signal will in most cases be an approximation of the signal you actually want, and you'll have to decide how good that approximation needs to be.

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  • \$\begingroup\$ Your suggestion to measure the input signal and use those measurements to create a new signal is a good approach. It may be worthwhile to note that a more fundamental question than "how good the approximation needs to be" is what the "correct" output should be if the input signal changes. As a simple example, if (sampled at 1us intervals) the input signal is ____----__--____----__-- should a double-speed version be __--_-__--_-__--_-__--_- or __--__--_-_-__--__--_-_-? Or perhaps _-__--_--_-__-__--_--_-_ or something else? \$\endgroup\$ – supercat Feb 28 '13 at 17:27
  • \$\begingroup\$ @DaveTweed: This approach works fine if the frequency of the input signal is low enough. But what if the input frequency is quite high, say of the order 1GHz or more ? (well, really sorry for that 10MHz in the image, will fix it :) ). For a reliable sampling and the subsequent DSP stuff, we'd require atleast a 10x clock to be fed to the FPGA; not quite practical at 1GHz.. \$\endgroup\$ – nav Feb 28 '13 at 17:41
  • \$\begingroup\$ What if it is? It's implicit in the question that whatever digital logic you're talking about is capable of handling both the input and output frequencies in question. \$\endgroup\$ – Dave Tweed Feb 28 '13 at 18:02
  • \$\begingroup\$ The issue is not about handling the output, but rather in sampling the input. To do so would require an additional faster clock, and that's something I don't have \$\endgroup\$ – nav Mar 1 '13 at 6:51
  • \$\begingroup\$ Why does the input need to be sampled, and what "DSP stuff" are you talking about? \$\endgroup\$ – Dave Tweed Mar 1 '13 at 12:09
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Feed a fast clock to two binary counters. Reset one counter on the + edges of the input signal. Reset the other on the - edges. As one resets, store the other's output into a latch. This way you measure the input's high and low periods, in proportion to the duty cycle, to the accuracy allowed by the fast clock, and it'll update quickly if the input signal changes rate or duty cycle. (On the downside, it may be too sensitive to random jitter, noise.)

Use an even faster clock to drive two more counters, corresponding to the input's two counters. As each reaches zero, trigger a flip flop according to which one zeroed. Reset that counter to the latched values of its matching input counter.

The flip-flop's Q output is your desired output.

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protected by W5VO Mar 1 '13 at 12:43

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