I have a microcontroller outputting a ramp signal on an I/O pin in PWM form. i.e. the duty cycle steadily increases from 0% to 100%, then drops to zero and repeats. After smoothing I end up with a sawtooth-like wave (except of course the sudden drop to zero takes a bit of time due to the filter).
My microcontroller code uses a 1kHz interrupt and upon every interrupt decides whether the output should be high or low based on a) the current progress through the ramp, and b) for how many interrupt cycles the output pin has already been high or low.
This is all fine and dandy, and it works well for my application, but I need a faster solution.
Something tells me this should be realizable with a pure logic circuit rather than with firmware code. After all, we have a steady clock pulse and a steady increase from 0% duty to 100% duty. But I'm struggling with the implementation concept.
Can anyone think of a way to do this with logic gates, so that I can write this onto an FPGA/PLD and have many (much faster) waves being generated?
NB: To complicate matters, frequency must be adjustable. In my MCU code this is as simple as having a variable representing how many samples the ramp should last for.