PLL and VCO example of a reference tone's frequency muliplied by 12000 to generate a master clock

Question

A free project RAM Platter Hybrid aims to generate a master clock from a tone which is 12000 times lower in frequency.

The reference tone is 1 kHz at its central frequency. It will have a minimum of 0 Hz and a maximum of around 5 kHz.

As the multiplier is 12000, the output master clock's central frequency is 12 MHz. The master clock will range between 0 Hz and 60 MHz. The output master clock can be tonal or rectangular. However a tone is preferred.

Is there a way to generate such a master clock from a low frequency reference tone using a VCO and PLL?

NOTE: This question is similar to the DDS based question but is asking for a PLL+VCO solution. NOTE 2: The original version of this question used a 1200 multiplier instead of 12000.

Answer 1

The main problem you have is the capture range and lock range. To use a PLL for a range of frequencies that approaches zero (repeat after me "it can't be zero") and then extends up to 5 kHz means, a massive undertaking in the design of the VCO. The VCO has to span a vast range of octaves to get even moderate performance and, the wider the range, the less accurate the output will be in terms of jitter and noise.

Consider a VCO on a music synthesizer; it might have a span of 7 octaves that takes you from (say) 20 Hz up to 1280 Hz. If you want 1 Hz (repeat after me "it can't be zero Hz") to near 5 kHz, that's over 12 octaves. Yes, with careful design and some degree of complication, a reasonably stable VCO can be designed to work from 1 Hz to 5000 Hz but, not cheap and not easy for a hobbyist (or even someone like me). I'd say a one month task simulating and building and testing at best (for me).

I see you have also got a little confused about what jitter means. Jitter is the inability of the VCO to stay at a perfect non-shifting frequency when the control input is absolutely stable. Now, this can be somewhat overcome by taking a long time in the PLL filter to "measure" the difference between input frequency and the current VCO frequency so, that "long time" means a slow response to changes from the turntable.

Inevitably, if you want speedy responses to the input frequency, you need to design a VCO with miniscule levels of jitter so that the PLL can use a quicker filter (without having to worry about filtering out jitter).

The VCO is key here so concentrate on this first. Make it stable, make it very stable. Test it to death and test it against temperature changes and power supply voltage variations or....

$$\color{red}{\text{Fundamentally revise your requirements}}$$

The master clock will range between 0 Hz and 60 MHz.

The upper limit is 1200 x 5 kHz = 6 MHz (a moot point really).

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Another thought - if you can machine a high precision physical markers along the edge of the platter (maybe 1,000 or even more) you could equate 1 revolution of the platter with 1,000 pulses from an optical sensor located at the edge of the platter. Or use a high precision optical encoder mechanically linked to your platter. Just a little brain-storming. It gets you a higher frequency range at the very least and that will significantly improve response time. At 33 rpm, you'll get 33,000 pulses per minute or 550 Hz. With an optical encoder you might get ten times this.

Answer 2

After some digging and guidance from Derek @ti.com the following is a good solution.

The common knowledge problem with jitter (which was pointed out in Andy aka's answer) is that there simply aren't enough cycles in the VCO to ensure that the signal is tracked accurately by the PLL+VCO. The solution is to use radio frequency design techniques to use a much higher frequency in the PLL+VCO and also to split the signal's frequency expansion over two stages.

The general design is as follows :

1. Enter a first RF stage to expand the baseband's bandwidth by 100.
2. Up convert the baseband signal to modulate a 10 MHz carrier
3. Use an RF band (1 GHz) PLL and VCO with an N=100 divider in loop to ensure that the PLL can track and the baseband signal's bandwidth is multiplied by 100 times.
4. Down convert the 10 MHz + 1 GHz signal back to baseband where we have an upper bandwidth of 500 kHz in the baseband's signal now.
5. Enter a second RF stage to expand the baseband's bandwidth by 120.
6. Up convert the baseband signal to modulate a 10 MHz carrier
7. Use an RF band (1.2 GHz) PLL and VCO with an N=120 divider in loop to ensure that the PLL can track and the baseband signal's bandwidth is multiplied by 120 times.
8. Down convert the 10 MHz + 1.2 GHz signal back to baseband where we have an upper bandwidth of 60 MHz in the baseband's signal now.