This is your homework/coursework, so this is to guide you, not to supply the answer. This information is all available on the internet.
You can see from the timing diagram that the X glitches occur when the outputs of DFF_A and DFF_B both change level, on the same clock edge.
You can then follow through the effect on the gates that DFF_A and DFF_B drive.
Remember that the model you have is trying to model real circuits as best it can. In real digital circuitry, the two DFF outputs will not change literally simultaneously from the same clock. There will be slightly different responses from each circuit, different propagation delays along the connection in and out of the DFFs etc. Models either ignore these delays completely or try to emphasise them by showing large glitches. Here, your combinatorial gate settling time shows the uncertainty in the outputs as both DFF outputs change across each other, one rising and one falling.
Glitches in combinatorial logic circuits are unwanted transient output states. They are caused when the inputs are at intermediate states before reaching their final states.
They are removed by:
Not having any unwanted input combinations. For example, by only having a single input change at any time and only from its previous level to a new final level.
By filtering the output. In synchronous logic circuits, this is usually by passing glitchy outputs through a further DFF. But this introduces a delay in the output of up to 1 clock so it may not be allowable.
You will have to think through this information and your circuit to find the solutions, explain them and justify them.
