Why does this BJT logic circuit only function intermittently?

Question

In my free time I've been trying to implement some simple logic gates and circuits using BJTs only (BC547s are the ones I have lying around).

The circuit

I've successfully built inverters, NAND and NOR gates. However I ran into trouble when I tried creating some sort of "latching" circuit. Here's the logic diagram:

Both A AND B need to be HIGH in order to turn on the output, but once it's on, A can go back LOW and Q will stay HIGH until A goes back LOW.
Here's what my attempt looks like using a NAND and NOR gate, each followed by an inverter:

The base resistors are 10k and the collector resistors are 1k, VCC is 5V

The Problem

The circuit works. Sometimes. When I first tried it out, it worked like a charm. All of a sudden it stopped working. It would get stuck in the HIGH state when it should have been LOW and the other way around. I found out that if that happened, I could "flip" it into the correct state by touching resistor R8.
I'm a 2nd year EE student, I know about digital circuits (only on the logic gate level, not how they're implemented) and a bit about BJTs.
I'd greatly appreciate if somebody could shed some light on this for me.
Thanks, and a happy new year :)

Answer 1

The problem is the PN junction from the base to collector or T4. When T5 is off, the emitter of T4 is floating. If you now apply a high voltage to the left end of R5, T4 acts like a diode from base to collector. This turns on T6 directly from the high output of T3.

Put another way, the NAND gate formed by T4 and T5 has a bug. It doesn't work when the T4 input is high and the T5 input low. Your overall logic was right, but due to T5 being off, T4 doesn't work like the transistor you are assuming anymore.

To make a NAND gate, just flip your NOR gate around using PNP instead of NPN:

By the way, this whole problem goes away if you use logic-level N-channel MOSFETS instead of NPN transistors. You can stack those and get what you intended.

Answer 2

The two transistors from R9 down are operating (obviously) as a NAND gate. Lets call the top one T4. (I just saw that it is; the schematic has the reference a little bit away from the device).

Here is where transistors (I have seen this for bipolars and FETs) can be a pit picky: they usually need a solid DC ground bias path and the current through R8 may or may not properly turn on (or off) T4 under all circumstances.

A large value resistor (100k or so) from the base of T4 to ground should cure the issue.

Assume the output is high (T4 and T5 are both on), and you take B low; that turns off T5, but there may be sufficient leakage T4 will still conduct; touching R8 is probably sufficient leakage parasitics to provide a DC bias path and all is well again.

Another possibility is that the resistors are not quite correctly sized; when the feedback comes around to T1, the transient current will be interesting. I will look more closely and update this in the morning.