What are the recommended CK, DQ, DQS, ADDR impedances for LPDDR4?

Question

I am using a micron part with LPDDR4, in many datasheets from micron there are no references to a specific impedance for CLK, DQ, DQS, ADDR. The datasheet mentions that the LVSTL is tuneable, but what is the nominal differential and single ended impedance for these PCB traces?

I have also checked the TN-53-06: LPDDR4/LPDDR4X Point-to-Point Design Guidelines from micron and it says this:

Standard characteristic impedance (Z0) of no more than 50Ω, nominally, is recommended for all traces. The 50Ω level also provides a good match to the output impedance of the SoC/FPGA memory controller drivers.

So are all the signals to be routed with 50Ω impedance?

Answer 1

I talked with a few more people, the answer is found in whatever LPDDR controller documentation the manufacturer of the device says it is. After talking with the manufacturer, they said, "Oh yeah there is more documentation we forgot to send outside of the datasheet." And that had all of the routing information in it. All of the documentation I could find on similar LPDDR4 controllers all had the routing information in the controller datasheet (NXP, Xilinks, TI)

Also the LPDDR4 interface is tunable so whatever is set off of Rzq can be a multiple of the recommended 240Ω impedance.

Answer 2

are all the signals to be routed with 50Ω impedance?

Maybe but NO, that is not sufficient to ensure adequate eye margin. It is important to get the scattering parameter (s-parms) from both the DDR supplier and uC or SoC supplier to guarantee impedance matching for both LVDS (95ohm) and DDR signals. The board dielectric choices affect insertion loss, loss tangent @ f, and slew rate and may contribute to edge dispersion and eye window margin loss. It is important to create a budget for each contribution to eye window (EW) margin loss.

The design rules are available from many suppliers incl; TI NXP Micron The board shop must verify the integrity of all traces with specified impedances using TDR "electrical tests" on your PO to your design specs.

You need to collect all device s-parms and material and design data to prevent impedance discontinuities, skew jitter, margin loss, dielectric loss skew, surface roughness skew, trace and via crosstalk, effects on inter-symbol interference (ISI) from frequency-dependent impedance, stub interference, match microstrip, stripline, and coplanar stripline impedances and run TDR and eye pattern simulations.

e.g. from TI

PCB design and material choices are critical at these frequencies because 50 Ohms is not 50 Ohms at all frequencies and can vary from 1mm to the next if there is less glass in the weave when parallel to the weave. RF signals travel through PCB material, and will experience loss and distortion due to Dk & Df, skin effect with a surface roughness of copper foil. For digital signals, this results in attenuation, pulse broadening, timing errors, and loss of window eye (WE) margin.

disclaimer:

This is the approach I would initiate if given the task to design with this technology to achieve low error rates and high window margin.

Also, review the web for existing 3rd party designs with revisions. e.g. https://www.96boards.org/documentation/consumer/aiml/hardware-docs/files/aiml-sch.pdf

Answer 3

Afraid I can't help with references.

But, if it happens that there's no firm answer to be found from relevant authorities, there's a possible explanation for that.

If you don't need source termination (or can compensate with external resistors to make up the total), signal quality is dominated by two things:

1. Consistency of the transmission line, not its absolute impedance;
2. Pin receiver impedance, in relation to Zo. Inputs generally being capacitive, so this creates an RC time constant, which needs to be a suitable fraction of a bit time to allow for the logic level to settle out before it is sampled.

Low impedances work in favor of #2, so keeping it on the low side is probably the recommendation.

Note, this all becomes much more sensitive if they're doing spooky things with the transmitter and receiver. Again, I don't know these interfaces in much detail, but I've read about such features as receiver transition blanking (ignore additional transitions within some ps of an initial edge), or transmitter preshoot (drive a spiky edge to compensate for PCB losses). There could also be built-in termination resistors; or lossy capacitances having a similar effect at high frequencies. Obviously, if any of these are done in terms of impedances, then their effects will vary with Zo, and staying close to recommended impedance will be most promising.