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enter image description hereI am working with a 4-layer board (Signal - GND - PWR - Signal).

The power layer uses routed power so that each chip's power rail can be isolated. Layers 1, 3, and 4 have ground pours and stitching vias. The ground layer is solid, so the routed power has a good return path on the adjacent ground. The stackup has the outer layers 0.065 mm separated from the adjacent layer, and power and ground are separated by 1.2 mm

The possible issue that I see is that the ground pour is over 18 times closer to the power trace than the dedicated ground plane. The coupling to the layer 4 pour is much greater than to the ground plane. Unfortunately the pour is interrupted by traces so that return current on the pour cannot fully follow the power trace.

I would think that when the return current on the pour is interrupted noise will be radiated inside the board. This board fails conducted voltage emissions.

To summarize, there are 2 return paths. One is closely coupled but interrupted. The other has less coupling but is properly decoupled on both ends.

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    \$\begingroup\$ Can you show a relevant part of the layout and specify the used currents and frequencies? It is hard to say something useful without. \$\endgroup\$
    – Jens
    Aug 8 at 19:04
  • \$\begingroup\$ The purple traces are on the power layer and the red traces are on the bottom layer which is 0.065mm away. The gnd layer has no voids, only via holes. \$\endgroup\$
    – SWM01
    Aug 8 at 21:28
  • \$\begingroup\$ I understand your idea, very fast switching, >10 A, could be relevant. I have never seen a board failing conducted emissions test for this reason alone. \$\endgroup\$
    – Jens
    Aug 8 at 22:05
  • \$\begingroup\$ What is your max current? Are you switching? At what frequency? Do you have a continuous ground? What conducted emissions test are you failing? \$\endgroup\$
    – Voltage Spike
    Aug 8 at 22:29
  • \$\begingroup\$ The application draws ~250mA so not high current. Frequencies of interest are 50MHz - 150MHz higher order harmonics are present but not the major problem. Layer #2 is a continuous ground with only via holes. Conducted voltage is failing but conducted current and radiated emission are marginal. \$\endgroup\$
    – SWM01
    Aug 9 at 16:53

1 Answer 1

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Multiple return paths are the usual case. But there is only one decisive one: the one with the smallest loop area and hence inductance. This is the dominant return path taken by (EMI relevant) high frequency current.

If your intended GND plane return path is too far away, that means the current will return through top layer copper. And this is the reason why your stackup often causes EMI issues, and frankly being a terrible stackup decision when the gap between the two inner layers is big.

Mitigation

  1. if possible with a stackup like yours, make both inner layers GND and route power between signals on the outer layers if space permits..That way both power and signals with excellent return loops and negligible coupling to eachother.

  2. use the power distribution only for low frequencies such as below 1 kHz, and take high frequency power only from local decoupling that has bottom layer GND close to L3 power. That way you at least solve the power return part. You will still need to care for all the signal on L4 running near the power layer. Make sure their return current are closed with capacitors. In the end, you may realize why (1) is actually often easier.

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  • \$\begingroup\$ I like the stackup you mentioned in item #1 and have used it in the past particularly for test / experiments boards. Unfortunately this board was designed by committee and I am only one of 3 contributors. I am trying to convince the team that we need to spin this board but I am unsure how much of a problem these power crossings are. If the decoupling were ideal there would be almost no high frequency noise on these traces. There are a number of other changes we would do in a spin but I am unsure about the consequence of the power return crossing. \$\endgroup\$
    – SWM01
    Aug 9 at 17:30
  • \$\begingroup\$ @SWM01 if you indeed have GND pours on L3 and L4 and stitching vias, then tracks crossing on L3 and L4 should be acceptable. because their return paths would still be in the nearby layer for the most part and only take a short detour through 2 stitching vias at a crossing. \$\endgroup\$
    – tobalt
    Aug 9 at 17:35
  • \$\begingroup\$ Understood and it makes sense from a circuits point of view. My confusion is from an RF point of view (not sure if this applies). You have a contained wave between L3 and L4 and or a wave between L3 and L2. The wave between L3 / L4 encounters an interruption and would radiate into the board. It is possible that most or all the energy travels in a wave the L3 / L2 medium. Does the discontinuity in the L3 / L4 path force this? This is where my question / confusion lies. \$\endgroup\$
    – SWM01
    Aug 9 at 18:21
  • \$\begingroup\$ @SWM01 if a L4 trace encouters a small gap in L3 copper, the E field will spread through that gap towards L2, but this is negligible. The major problem (potentially an absolutely fatal one in EMI tetms) is that L3 doesn't offer a tight return current path anymore. If you provide a nearby return current path through stitching vias and L4 pour, this is mitigated. Still this is worse (and a needless complication) than simply routing over solid L3 copper, which is my recommendation #1. \$\endgroup\$
    – tobalt
    Aug 10 at 4:37

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