I am working with a 4-layer board (Signal - GND - PWR - Signal).
The power layer uses routed power so that each chip's power rail can be isolated. Layers 1, 3, and 4 have ground pours and stitching vias. The ground layer is solid, so the routed power has a good return path on the adjacent ground. The stackup has the outer layers 0.065 mm separated from the adjacent layer, and power and ground are separated by 1.2 mm
The possible issue that I see is that the ground pour is over 18 times closer to the power trace than the dedicated ground plane. The coupling to the layer 4 pour is much greater than to the ground plane. Unfortunately the pour is interrupted by traces so that return current on the pour cannot fully follow the power trace.
I would think that when the return current on the pour is interrupted noise will be radiated inside the board. This board fails conducted voltage emissions.
To summarize, there are 2 return paths. One is closely coupled but interrupted. The other has less coupling but is properly decoupled on both ends.