I often see op-amp's modelled with a finite output impedance or resistance as follows:
Let's assume that the op-amp above is implemented with the following structure:
From the transistor level diagram, how can the model say that there is an Rout in series? Is it referring to the small-signal output impedance of M5 in parallel with Mb4 rout?
In short, what is the origin of this Rout in the model diagram from a circuit perspective?
From the transistor level diagram, how can the model say that there is an Rout in series?
That model is a generic one, based on the fact that it is (A) practically impossible to build any amplifier with zero output impedance, and (B) op-amps are generally not designed for low open-loop output impedance.
The entire point of an op-amp is that the things that matter in closed-loop -- being the gain, the gain-bandwidth product, the input offset, etc., are optimized, and everything else is pretty much left to find its own value. Output impedance is one of those things that get left to find its own value.
Is it referring to the small-signal output impedance of M5 in parallel with Mb4 rout?
In that particular schematic, yes. But in practical terms, all op-amps have fairly high output impedances because it generally doesn't matter. Sometimes it does, and then you have to pay attention. But usually it doesn't (or you can work around it) and then you can ignore it.
The series output resistance is the Thevenin equivalent resistance looking into the output, essentially, the drain-source resistance of the output FETs.
If the FETs are modeled correctly, then the op-amp output resistance will also be modeled correctly.
