To your first question: Yes. There is a low pass filter buit in. This avoids the "aliasing trap" of ADC conversions.
Signal input frequencies close to and above the sampling rate appear as much lower frequencies in the conversion results.
Imagine a square wave signal with 5 times the sampling rate. A sample is a momentary snapshot of the input. For a while (some samples) you may hit the input signal during high periods, then for another while, you hit the signal at low periods.
The array of sampled values now contains a group of high voltages followed by a group of low voltages. This can only be interpreted as, or looks like a square wave signal with a frequency far below the sampling rate, the "alias" frequency.
Antialiasing filters are always needed in front of ADCs, either explicit or implicit by the limited bandwith of the signal source.
To your second question: Yes and no. You define the sampling rate, because you create the trigger pulses at the CONVST inputs. The sample and hold circuits take a snapshot of the input voltages after the rising edge of this signal. Then the conversion process is busy.
You can pick up the conversion results after busy becomes low, either using the parallel interface, the splitted serial interface with two data out lines or the non splitted serial interface with one data out line.
The transfer duration of the used interface determins the time, where the next CONVST pulse can be placed.
So using the non splitted serial interface may limit the sampling rate, the parallel bus won't.
If you configure oversampling, the ADC will perform multiple conversions after a single CONVST pulse and the delivered results are the average of these conversions.
So, as I understand the datasheet, you cannot place CONVST pulses while the averager is working. The sampling rate is reduced, see Table 9 of the datasheet.