I'm using an AD7606-4 which is connected to an STM32 EVB.

The connection is in the serial configuration and samples only 4 channels (DOUTA only).

The sampling rate in the datasheet is 200 ksps, but I can't understand if that is in the parallel or the serial configuration.

  1. The datasheet makes me more confused: "The AD7606-EP antialiasing filter has a 3 dB cutoff frequency of 23 kHz." What is the meaning? The maximum analog signal that I can sample is ~11 kHz?
  2. Is there any difference between the sampling rate of the parallel and the serial connection?

EDIT : Im reading right now the REF Manual and try to understand what is the meaning of this graph enter image description here if the sample rate is 200kSPS what is the meaning of AAF in frequency of 15kHz??? what I'm missing?

  • \$\begingroup\$ Refer to The Fine Manual and you'll find that ADC conversions are initiated using the CONVST pins. So you decide what the sampling rate is and apply an appropriate control signal to those pins. \$\endgroup\$
    – brhans
    Nov 15, 2022 at 15:40
  • \$\begingroup\$ how can I decide the sampling rate with the Convst? \$\endgroup\$
    – Knowledge
    Nov 15, 2022 at 21:30
  • \$\begingroup\$ Did you read the relevant part of the Manual? Did you understand what the CONVST pins do? \$\endgroup\$
    – brhans
    Nov 15, 2022 at 22:46
  • \$\begingroup\$ Re your new edit: the sampling rate (maximum 200kSPS) and the anti-aliasing filter (15kHz at +/-5range) are not related. Why do you think you're missing something? What's wrong with having a 15kHz filter and 200kSPS sampling rate? \$\endgroup\$
    – brhans
    Nov 19, 2022 at 1:15
  • \$\begingroup\$ @brhans if I want to sample analog signal with 50kHz, the AAF will cut off the signal in one side. in the other side the sample rate is 200kSPS so it looks like I can sample signal with 100kHz, what I miss? thanks \$\endgroup\$
    – Knowledge
    Nov 20, 2022 at 10:32

1 Answer 1


To your first question: Yes. There is a low pass filter buit in. This avoids the "aliasing trap" of ADC conversions.
Signal input frequencies close to and above the sampling rate appear as much lower frequencies in the conversion results.
Imagine a square wave signal with 5 times the sampling rate. A sample is a momentary snapshot of the input. For a while (some samples) you may hit the input signal during high periods, then for another while, you hit the signal at low periods.
The array of sampled values now contains a group of high voltages followed by a group of low voltages. This can only be interpreted as, or looks like a square wave signal with a frequency far below the sampling rate, the "alias" frequency.
Antialiasing filters are always needed in front of ADCs, either explicit or implicit by the limited bandwith of the signal source.

To your second question: Yes and no. You define the sampling rate, because you create the trigger pulses at the CONVST inputs. The sample and hold circuits take a snapshot of the input voltages after the rising edge of this signal. Then the conversion process is busy.
You can pick up the conversion results after busy becomes low, either using the parallel interface, the splitted serial interface with two data out lines or the non splitted serial interface with one data out line.
The transfer duration of the used interface determins the time, where the next CONVST pulse can be placed.
So using the non splitted serial interface may limit the sampling rate, the parallel bus won't.
If you configure oversampling, the ADC will perform multiple conversions after a single CONVST pulse and the delivered results are the average of these conversions.
So, as I understand the datasheet, you cannot place CONVST pulses while the averager is working. The sampling rate is reduced, see Table 9 of the datasheet.

  • \$\begingroup\$ please look at my new edit , \$\endgroup\$
    – Knowledge
    Nov 16, 2022 at 20:53

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