I'm connecting a PIC18F46K22 (master) to a PIC18F4620 (slave) using I2C. The wire between the devices is ~30cm. I'm using 400kHz without slew rate control. Later on, I'll add another 18F4620 on ~5cm from the master (~35cm from the other slave).
How do I calculate the pull-up resistance needed on both the SCL as the SDA line?
Does it matter where I place the pull-up (near the master, near the slave, both, in the middle, ...)?
The pull-ups are generally located near the master device.
This app note goes into some of the calculations. Essentially, the size of the pull-up will be defined by the total bus capacitance and the pull-down capabilities of the devices on the bus:
\$ R_p \ge \dfrac{V_{dd}-V_{OL}}{I_{OL}}\$
and
\$ R_p \le \dfrac{300ns}{0.847298 \times C_{bus}}\$
where \$V_{OL}\$ is the logic low voltage needed, \$I_{OL}\$ is the sinking current, and \$C_{bus}\$ is the bus capacitance.
Of course, once your sample is built, the best thing to do is scope the waveforms and make whatever adjustments are needed.
When the line is pulled low, the driver pin (SCL on master, or SDA on master or slave) supplies current V/R to do that; so if it's a 10k resistor from 5V, the driver will need to sink 0.5 mA. A larger resistor means less current is needed, but the line will pull up more slowly (especially on a long line) and this may limit your rate. A smaller resistor pulls up faster, but at some point you'll burn out the driver pin (check the data sheet). 3.3K to 10K is probably fine; if it's 3.3V maybe 2.2K-4.7K
It doesn't matter much where you put them electrically, but near the master is better if the cable might be disconnected; or you could put e.g. a 10k pullup at each end, instead of a single 4k7, which will keep both ends happy when the cable is disconnected.
Generally, for cable lengths to +-20cm, SCL at 100kHz will be happy with 10k. With increasing frequency and/or length, you may go as low as 1k.
