I am having trouble getting the voltage Vout=1.25v and the gain should be Av=5 and I have the input voltage Vin = 0.25v. This is my schematic, what did I go wrong?
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\$\begingroup\$ @Ma5assik, You've got some useful responses already. But when you ask "where did I go wrong?" you need to say a little something about your thinking process in creating what you have. Otherwise, it's difficult to help you pin down where you went awry. Could you talk a little about your design process? \$\endgroup\$– periblepsisCommented Oct 15, 2023 at 3:58
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2 Answers
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Your biasing is way off. You want the DC voltage at the collector to be roughly half the supply voltage.
It looks like you're going for 1 mA collector current since you're using a total of 12 k for \$R_E\$ and \$R_C\$. At 1 mA you'd have around 2 V across \$R_E\$, so the voltage at the base should be that plus \$V_{BE}\$, call it 2.7 V.
Your divider works out to: $$ 24 V\times \frac{2k}{2k + 8k} = 4.8 V $$
So way too high. You want 2.7 parts out 24, so make R2 some multiple of 2.7 such as 2.7 k, then the total resistance has to be the same multiple of 24, or 24 k. Subtract R2 from 24 k to get R1, 21.3 k, call it 22 k for a standard value. This gets you: $$ 24 V\times \frac{2.7k}{2.7k + 22k} = 2.62 V $$ Which is much closer to what you want.
A simulation with these values in LTspice gets me a collector voltage of around 14.2 V and a nice looking sine wave output of about 1.2 VRMS. With the original values I got collector voltage of 4.17 and a very distorted output of around 735 mV, so just this simple change made it much better.
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As reflected in the previous answer, the base biasing is too high.
Increase R1 to 13k. This will reduce the base bias, reduce the emitter bias, reduce the emitter (and collector) current thereby increasing the collector bias to about 12 V or so.