Why doesn't this amplifier work?

Question

I'm trying to understand how this circuit (a low-noise amplifier) works from this paper. According to my understanding, the first stage is a class AB amplifier and the second stage is a simple follower. Capacitive coupling is used to block low-frequency noise, and DC biasing is added through the feedback of an opamp. The 4 capacitors are also used as negative feedback to set the gain.

I built the first stage in Cadence and tried to simulate it. However, I got almost nothing from the output (tens of micro-volt signal). gm1 and gm2 are both about 8uS, and the output impedance of M1 and M2 are about 50M Ohm. So I was expecting a gain of 400x.

I ran a transient simulation and found that the signal at the gate of M1 and M2 are in opposite phases. I was wondering if this was the reason of the problem, as M1 and M2 should receive nearly identical inputs to work properly? How can I fix it?

Answer 1

This circuit works OK when built from junkbox parts, so if the simulation doesn't work, it's the simulation's problem. I've built it with a 12 V supply, discrete small signal MOSFETs, and LM334s set to 1 mA as current sources. Worked on first try, with a series resistor on the output of the op-amp.

The mistake you made in simulation is not using a low-conductance-output discrete op-amp model. The circuit was drawn without a series resistor on the op-amp's output because it's easy to control output resistance of an op-amp with device geometry when you're designing an IC. The on-chip op-amp's output would be inherently weak. You used a generic op-amp model that doesn't represent any particular op-amp that could be built in the process node you chose.

Answer 2

I'm not going to deny that it took a while to understand this amplifier, but I think it should work.

I've made some annotations to the schematic to guide the explanation better.

First, the 1st stage appears to be class-AB as you said, since, at AC, \$V_{in}\$ appears at the gate of both \$M_p\$ and \$M_n\$ transistors.

Now the biasing is the more interesting part. You might have learnt that you must put resistive feedback around an amplifier with capacitive feedback such that there's DC feedback around the amplifier, i.e. to keep all transistors biased properly.

This is not necessary in this amplifier because the biasing has been done locally. For example, the gate of \$M_p\$ is well-defined due to the diode connected transistor biased with a current source; \$V_{gp}\$ is then well-defined. However, this does nothing to the drain of \$M_p\$; because this is handled by op-amp, whose (-) terminal is fixed at 0.5Vddreg (Vddreg being the output an LDO regulator, I presume). This op-amp will do anything to keep its inputs equal, and in this case it'll control the gate of \$M_n\$ to achieve this purpose.

So far, we have the biasing of the 1st stage solved.

The 2nd stage is a common-drain amplifier (or better said, a buffer). Its voltage gain is 1, and since it is, fundamentally, a local shunt-series (output-input) feedback stage, it just needs a well-defined DC at its input, which it does since it is connected to the input of the op-amp mentioned previously.

Now, the capacitive feedback is used to define the gain. The gain should simply given by \$-\frac{C_1}{C_2}\$ (yes, the opposite of a resistive-feedback inverting amplifier).

Your schematic does not include the last stage with the capacitive feedback, so I don't expect it to work as the paper. With some luck, perhaps you see the the input signal at the output with a gain of 1. However, you have to keep in mind this is a 65nm technology. Are you using the same process node, at least? Are your transistors in weak inversion at least? What about their vdsat margin before they become switches? What amplitude of a signal did you input? Could it be that there's cross-over distortion at the voltage level you're trying to amplify, thus there's little gain in practice?

That much I could infer without the paper and only by looking at the schematic. Once I read the paper, I found that this is supposed to be a non-linear analog frontend to extract acoustic signal from sensors, and the selling feature is that its exploiting non-linear analog signal process (and for an amplifier, non-linear means an small loop gain, thus lots of power savings). For instance, it is said that the error amplifier is biased at 15.5pA. I have no clue how such a thing is implemented, perhaps at a really deep weak-inversion with a small device (?), no idea.

So, the question is: are you really working on the same application to be asking about how this amplifier is supposed to work?

Finally, a word about publications and pipe-dreams, as a commenter said above. While it is true that there many low-quality magazines that publish a lot of rubbish (and I have criticized and downvoted answers that cited such rubbish pubs in this site), a click on the link would've sufficed to find out that the publications is under the JSSC, which does not publish anything without measurements on silicon, which keeps the bar quite high.

EDIT:

The other poster is right about the need of the resistor, and clearly because you said it works for you. I guess he explains his own way, but to me it is clearer to say that the outputs of both error amplifier and \$M_{ps}\$ are fighting against each other at signal frequencies (they're, basically, shorted together), and if the error amplifier is ideal, then \$M_{ps}\$ doesn't have the strength to drive the virtual ground because any current being output is eaten away by this error amplifier, thus your gain is degraded.

I totally missed this in my first view of the amplifier.