This is a full bridge circuit which I am trying to simulate in Ltspice with a snubber. When I use ideal switches instead of MOSFETS, the simulation works fine. But when I use the real mosfet models, the simulation takes a lot of time for the transient analysis. What changes should I make to make it work?
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2\$\begingroup\$ That top node looks a little floaty. Is there supposed to be a voltage source there? \$\endgroup\$– periblepsisCommented Feb 2 at 11:43
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\$\begingroup\$ The RCD network seems to be connected across the output capacitor which sees dc? \$\endgroup\$– Verbal KintCommented Feb 2 at 12:49
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\$\begingroup\$ The top switches won't be able to turn unless you only have a few volt on your DC bus, since the gate drive is referenced to ground instead of source. \$\endgroup\$– winnyCommented Feb 2 at 13:13
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\$\begingroup\$ @periblepsis It's in reverse, a rectifier. \$\endgroup\$– Tim WilliamsCommented Feb 2 at 13:18
1 Answer
Two significant errors.
Well, maybe the one is intentional, I don't know what you're really trying to simulate here, you haven't exactly given us a complete specification what you're doing here -- but from the basic description, it sounds like it would be an error.
Capacitors in series: singular matrix error. C1-C4 create two floating nodes, the voltage of which cannot be solved from the circuit matrix as given; the voltage is a free variable, with no unique solution (the degree(s) of freedom are described by the matrix's null space.) Typically, simulators set a default RSHUNT which shorts this out, but from timestep to timestep, the near-singular matrix can take quite long to invert, or push timesteps very low, either way the simulation runs very slowly indeed.
It's just a simulation, physicality is irrelevant (LTSpice also isn't an complete EDA tool, it's not like you'll be exporting the netlist to a PCB unmodified--?). Use single equivalent components, no need for series or parallel connections.
Also, mind parasitic parameters: components may not be exactly as shown; with no other labeling, I have to assume components are [purely as shown], but I can't know for sure. New users often miss this, so, I'm just adding this for completeness. I suggest not using parasitic parameters at all (set them to zero or null) and showing all elements on the schematic.
Gate drive must be referenced to source. U1, U3 are acting as source followers, but as the legs of the H-bridge are being driven by voltage sources (plus some inductance), they can never turn on (Vgs is about -18V or -10 during a pulse, I guess).
The risetimes are nonphysically small. I am not aware of any gate driver which offers 10ps edge rates, and one would be, honestly, dangerous to use in most any kind of circuit, not to mention useless given typical circuit dimensions. Keeping this to a more realistic 5-50ns allows the simulator more time to compute the rapidly-changing dynamics around each switching edge.