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I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.

I am struggling to comprehend how the stages are counted. While some designs I've looked at are said to have three stages, I always seem to count at least four.

Here are two examples:

Annotated CPU datapath

Annotated CPU datapath

I've carefully annotated both images with my comprehension of the pipeline stages. In both designs, the instruction and data memories are synchronous, leading me to believe that three implicit pipeline stages have already been created. Thus, adding another pipeline location would lead to the creation of a fourth stage.

What am I getting wrong in this analysis?

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  • \$\begingroup\$ Have you followed classic theory of computer architecture, like Hennessy and Patterson textbook? The stages are not named as "Stage ##", but by their function. The classic pipeline is "fetch"-"decode"-"execute"-"complete"-"retire". - five stages. Do they want you to invent something new? \$\endgroup\$
    – Ale..chenski
    Commented Aug 12 at 2:55
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    \$\begingroup\$ Yes, they've introduced the classic five-stage RISC pipeline, @ale-chenski. For this project, I'm specifically asked to do a three-stage pipeline (no specifics on how to divide them). I've named "Stage #" just for clarity and because the David & Sarah Harris textbook I'm following also uses this for generic circuits. \$\endgroup\$
    – TheGMX
    Commented Aug 12 at 3:25
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    \$\begingroup\$ Where did you get these diagrams? I'd like to see them in context. \$\endgroup\$
    – Dave Tweed
    Commented Aug 12 at 23:57

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In your diagram, stage #1 and stage #2 occur in parallel. In other words, the logic that determines the next PC value is happening at the same time as the instruction decode and register access. Therefore, they don't count as separate stages in terms of the instruction pipeline (execution latency).

Basically, the number of stages is the number of registers, and your diagram identifies three sets of pipeline registers.

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  • \$\begingroup\$ Would you mind to elaborate, please? If I understood correctly, it isn't considered separate stages because as soon as the instruction is fetched from IMEM and starts to get decoded (#2), stage #1 is also updated (it does not depend on other stages). Is this right? If so, wouldn't the same be valid for stages #1/#2 and #4? i.e., the writeback happens in parallel to a NextPC (IF) update, and the latter does not depend on the former. I was under the impression that, as soon as you have a pipeline register (the IMEM), it becomes two separate stages. \$\endgroup\$
    – TheGMX
    Commented Aug 12 at 17:41
  • \$\begingroup\$ Well, yes, all of the stages do operate in parallel, but on different instructions. The writeback stage is working on the instruction that occurred two cycles before the instruction currently in stage #2. The way you've labeled it, stage #1 and stage #2 are processing the same instruction at the same time, so architecturally, they're the same stage. \$\endgroup\$
    – Dave Tweed
    Commented Aug 12 at 21:31
  • \$\begingroup\$ Sorry, I don't know if I'm following. Since the memories are synchronous, wouldn't stages #1 and #2 process different instructions? The NextPC mux sets the IMEM/BIOS input on a cycle (stage #1). In the next cycle, the instruction is released through its output for decoding (stage #2). The first diagram labels "pc_if" and "pc_id". Are they just different names for the same thing? \$\endgroup\$
    – TheGMX
    Commented Aug 12 at 22:47
  • \$\begingroup\$ Effectively, yes. PC_id is the actual output of the register. PC_if isn't another register; it's simply the result of combinatorial logic (mux, adders, etc.) being applied to PC_id, so it's all the same stage. Furthermore, the actual instruction fetch in "BIOS ROM" or "IMEM" is also part of that stage, because the next register you hit is actually at the outputs of those memories. \$\endgroup\$
    – Dave Tweed
    Commented Aug 12 at 23:43

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