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I need to use SPI and EXTCLK simultaneously in ATtiny 0/1-series (SOIC-8) and as you know PIN7 (PA3) functions EXTCLK/SCK. is there any way or trick to multiplex SCK to other pin?

Thanks for any suggestions. Ata

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  • \$\begingroup\$ The reply is undoubtedly explicitly written in the specific device data sheet. Do you take a look at? \$\endgroup\$
    – user317139
    Commented Nov 1 at 21:54
  • \$\begingroup\$ Yes i read it; there is no ordinary way. However, i assume maybe there is a trick to do it. \$\endgroup\$
    – Ata
    Commented Nov 1 at 21:59
  • \$\begingroup\$ What do you intend to link? \$\endgroup\$
    – user317139
    Commented Nov 2 at 9:56
  • \$\begingroup\$ Did you consider "reroute" SPI clock using LUT to PA6 or PA7 (LUT0-OUT and LUT1-OUT)? \$\endgroup\$ Commented Nov 25 at 18:19
  • \$\begingroup\$ @MichalDudka may you please explain it more? Or recommend any related application note about it. \$\endgroup\$
    – Ata
    Commented Nov 26 at 19:38

3 Answers 3

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SPI is very easy to bit bang. You can do it in software on any two pins.

There are many software libraries that will do this. Pick one depending on if you need SPI master or slave. Or write your own, it is a very simple protocol.

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  • \$\begingroup\$ The linked example is not about bit banging SPI… \$\endgroup\$
    – user317139
    Commented Nov 2 at 9:56
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There is one tricky way. Consider Attiny402, External clock 2MHz. PA1 as MOSI, PA3 as clock input (EXTCLK), PA7 as "rerouted" SPI SCK output. Trick is routing SPI SCK internaly to CCL LUT, configure LUT to pass SCK to its output.

#define F_CPU 2000000 // my External clock frequency
#include <avr/io.h>
#include <util/delay.h>

int main(void)
{
    _PROTECTED_WRITE(CLKCTRL.MCLKCTRLA,CLKCTRL_CLKSEL_EXTCLK_gc);
    PORTA.DIRSET = PIN7_bm; // LUT1_OUT as Output
    PORTA.DIRSET = PIN1_bm; // MISO as output
    
    // Set LUT1 INSEL0 input as SPI0 (SCK), other two inputs to "mask" (logical 0)
    CCL.LUT1CTRLB = CCL_INSEL0_SPI0_gc | CCL_INSEL1_MASK_gc;
    CCL.LUT1CTRLC = CCL_INSEL2_MASK_gc;
    // Set thruth table to copy INSEL0 value
    CCL.TRUTH1 = 0b10; 
    // Enable LUT and its output (PA7)
    CCL.LUT1CTRLA = CCL_OUTEN_bm | CCL_ENABLE_bm;
    // Enable CCL
    CCL.CTRLA = CCL_ENABLE_bm;
    
    // Setup SPI as Master (with buffer if you need)
    SPI0.CTRLB = SPI_SSD_bm;
    SPI0.CTRLA = SPI_MASTER_bm | SPI_ENABLE_bm | SPI_PRESC_DIV4_gc;
    
    while (1) 
    {
            SPI0.DATA = 0b11110110; // transmit data
            while(!(SPI0.INTFLAGS & SPI_IF_bm)){} // wait until transmited
                _delay_ms(1); // do some pause
    }
}

If needed, LUT output can be again "rerouted" to EVOUT0 (PA2) using event system.

Tested: enter image description here

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For 20-pin AT 0/1 series, SCK can be remapped from PA3 to PC0 (see datasheet 5.1 Multiplexed Signals). Multiplexed Signals for ATtiny 0-series This however does not available for 8-pin and 14-pin chip. You will need to use 20-pin chip instead of 8-pin chip if you need both SCK and EXTCLK signals.

Multiplexed Signals for ATtiny 0-series 8-pin chips

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