Search Results
Search type | Search syntax |
---|---|
Tags | [tag] |
Exact | "words here" |
Author |
user:1234 user:me (yours) |
Score |
score:3 (3+) score:0 (none) |
Answers |
answers:3 (3+) answers:0 (none) isaccepted:yes hasaccepted:no inquestion:1234 |
Views | views:250 |
Code | code:"if (foo != bar)" |
Sections |
title:apples body:"apples oranges" |
URL | url:"*.example.com" |
Saves | in:saves |
Status |
closed:yes duplicate:no migrated:no wiki:no |
Types |
is:question is:answer |
Exclude |
-[tag] -apples |
For more details on advanced search visit our help page |
A flip-flop or latch is a circuit that has two stable states and can be used to store state information.
2
votes
2
answers
3k
views
How to calculate latency of a circuit?
Lets say we have this circuit:
tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns
FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns
First I want to check this circuit for hold- …
2
votes
1
answer
130
views
Implementing a Mealy Machine in Verilog
I have a piece of code that I don't understand:
always_ff @(posedge CLK)
state <= RST || ~A[0]===1'bx || ~A[1]===1'bx ? 0 : nextstate;
A is the input. What is this piece of code exactly doing? What …