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edit approved Jul 7, 2014 at 8:22
Roh
edit approved Jul 7, 2014 at 8:22
Roh
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How to simulate PCIe to debug my fpgaFPGA endpoint

ImI'm working on an fpgaFPGA controller connected through pciePCIe. The only way iI can debug the hardware is using chipscope. So iI execute commands through my driver and check out the signals from the fpgaFPGA.

The problem is that it takes a lot of time to build the project and load it to the fpgaFPGA every time iI want to check a signal to debug the project.

Is there an easier way to debug an fpgaFPGA connected to pciePCIe?

Is there a way iI can simulate all the pciePCIe signals and not have to run the fpgaFPGA at all?

To be more specific, iI would like some kind of infrastructure that iI can write a command through the linux driver (writeq) and tlpTLP packets would be sent to my verilog design..

How to simulate PCIe to debug my fpga endpoint

Im working on an fpga controller connected through pcie. The only way i can debug the hardware is using chipscope. So i execute commands through my driver and check out the signals from the fpga.

The problem is that it takes a lot of time to build the project and load it to the fpga every time i want to check a signal to debug the project.

Is there an easier way to debug an fpga connected to pcie?

Is there a way i can simulate all the pcie signals and not have to run the fpga at all?

To be more specific, i would like some kind of infrastructure that i can write a command through the linux driver (writeq) and tlp packets would be sent to my verilog design..

How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA.

The problem is that it takes a lot of time to build the project and load it to the FPGA every time I want to check a signal to debug the project.

Is there an easier way to debug an FPGA connected to PCIe?

Is there a way I can simulate all the PCIe signals and not have to run the FPGA at all?

To be more specific, I would like some kind of infrastructure that I can write a command through the linux driver (writeq) and TLP packets would be sent to my verilog design..

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yonigo
yonigo
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How to simulate PCIe to debug my fpga endpoint

Im working on an fpga controller connected through pcie. The only way i can debug the hardware is using chipscope. So i execute commands through my driver and check out the signals from the fpga.

The problem is that it takes a lot of time to build the project and load it to the fpga every time i want to check a signal to debug the project.

Is there an easier way to debug an fpga connected to pcie?

Is there a way i can simulate all the pcie signals and not have to run the fpga at all?

To be more specific, i would like some kind of infrastructure that i can write a command through the linux driver (writeq) and tlp packets would be sent to my verilog design..