How does this inverter make the AND-gate better?

Question

I am very new to electronics and just started learning about logic gates.

I read about the AND gate and learned about its boolean algebra, but I also wanted to make one myself using MOSFETs which I learned about earlier. The AND-gate I made was pretty much identical to the one in picture 1. The only difference is that mine was implemented in an entire circuit. But I will use this picture because it's simpler and illustrates the problem more clearly.

Not sure if this was a good (or best) way to create an AND-gate using MOSFETs I started looking on the web for optimal constructions. Then I found this earlier post on engineering exchange which is very much a similar question to mine. However, it did not help me because I did not actually understand the explanations. This is because the explanation was meant for people with more advanced knowledge.

There is a picture of the AND-gate with the inverter below:

Here are my questions:

1. Could you explain to a less knowledgeable person in electronics why the AND-gate is improved by adding the inverter?

2. Is this inverter trick normally used in other types of logic-gates?

3. Is this AND-gate design using the inverter considered the "best AND-gate design" or are there multiple different designs for different use cases?

4. This is somewhat similar to question 3: Is there a generally considered best design for all the different logic gates? Is there a way to prove logic-gate design x is more efficient than all the other ones? Or does it mostly come down to price when producing them as long as it gets the job done?

Answer 1

1. It's an AND gate made with NMOS transistors. You can't make an AND gate unless you invert the output of a NAND gate, and you can't do an AND gate directly with NMOS transistors.

2. Yes, either on inputs, or output, or both, to build the logic function you want. For example for the same reason, you can do an NMOS NOR gate and invert the output to build an OR gate, because you can't build an OR gate directly with NMOS transistors.

3. If you only want an AND gate that works in isolation, it is the most simple circuit that happens to work adequately so that why it is the best. If you are building a complex logic equation with a lot of inputs and intermediate results, you use the simplest circuit that does the task adequately, and you would not draw separate instances of separate logic gates, because it's wasteful to add transistors that could be simplified away.

4. The best way is to use just the amount of circuitry needed to perform the needed logic function. You can't simplify a chip which needs to provide AND gates, but you can simplify a chip that needs to do a complex logic function with multiple inputs.

And what you might now be aware is that this only talks about NMOS logic, similar rules apply to PMOS logic, for CMOS the NAND gate would have both NMOS and PMOS transistors and inverter has two. And these are for static logic devices, if you have a system with a clock signal, you can make a more efficient system with less transistors if you use dynamic logic.