Signal-driven 3 output logic gate decoder or switch?

Question

I need to build a simple logic gate circuit such that when a single input signal or switch goes low it alternately activates one of three outputs as high. That is, every time it goes low the currently high output goes low and the next in the series goes high - cycling which output goes high between the three.

Years ago when I took an electronics class we used a program similar to CircuitLab. And I designed a very similar circuit. But I've lost that design and it was so long ago that I've gotten very rusty.

However, I can think of one way to build a circuit that would -almost- do what I want:

I could use a binary counter in combination with a 2-to-4 line single-bit decoder. (See the illustration on Wikipedia's decoder page.) The problem with that solution is it cycles between FOUR outputs. And my design requires that it cycles between only three.

As I said, I designed a circuit almost exactly like this years ago. And while the details are very foggy, I seem to recall that it was so simple that it only required one or more flip-flops (or latches) and a few other gates besides.

Answer 1

A simple circuit can be built using a 4017 counter.

The circuit normally counts 10 input pulses but by connecting the next output to the reset input via a small signal diode (eg. 1N4148) the 4th count resets the circuit to 0. It also allows you to expand the circuit very easily.to more outputs if required.

Edit (additional)

As OQ requires change when switch or signal input goes low then the clock input needs to be inverted. This can be easily accomplished with a single PNP transistor. A 100R resistor has been added in series with the switch to prevent it getting 'sticky' when discharging the capacitor (see Spehro's comment).

Also added the 10k between D1 and C2/R3 to the original circuit.

Answer 2

It's fairly straightforward. If you use a counter with an asynchronous reset, use the 4th decoder output to reset it. This will provide a very brief period when the counter is in the invalid 4th count. IF the counter has a synchronous reset or a synchronous load function, use the 3rd output of the decoder to assert that function (in the case of a synchronous load, load to zero). Then, when the counter output is 2 the next transition will be to zero.

Be aware that if you go the asynchronous route, you need to be aware of the possibility of skew errors in the decoder producing a false pulse long enough to reset the counter during one of the counter transitions other than the one you want. The asynchronous approach does not have this (potential) problem.