Clock distribution gone wrong

Question

I have had EMI problems in the past and I have decided to implement clock distribution with termination.

I have a 25 MHz crystal that travels through a 50 \$\Omega\$ strip in the PCB and splits into two. After the split the strips have an impedance of 100 \$\Omega\$. Each strip goes to an IC and then is terminated with a 100 \$\Omega\$ resistor to ground. I copied the idea from a book. (High speed digital design. A handbook of black magic)

When I turn on the board, I noticed the ICs don't operate well as they miss clocks. When I remove the terminating resistors all is ok. I am trying to do a good job to prevent problems with EMI.

What am I missing?

Answer 1

It sounds like your oscillator is designed to drive a CMOS load. With the load you gave it, it has to produce 66 or 100 mA to reach a high voltage (66 mA for 3.3 V, 100 mA for 5 V), and it's probably not designed to do that.

One option is to terminate with the equivalent of 100 ohms to Vcc/2:

^{simulate this circuit – Schematic created using CircuitLab}

This reduces the output current required from the source by half.

Even better, if you're able to do it, is route the signal past the two loads in sequence and terminate only once. Since you're able to produce 100 ohm tracks, use that geometry for the whole path:

^{simulate this circuit}

This reduces the current demanded from the source by half again.

Of course it's also possible to add a buffer amplifier that can drive the relatively low impedance of your load, but that adds components you might not have budget or space for.

Answer 2

This is too late, of course, since you've already awarded points, but The Photon is mistaken. You can do what you want without the power loss entailed by termination.

The technique you want is called series termination. This is (sort of) The Photon's technique minus the capacitor. At the output of the oscillator you put a 50 ohm resistor to match the 50 ohms associated with the trace. You then remove all your other termination resistors.

See, for instance, http://www.ti.com/lit/an/scaa045a/scaa045a.pdf page 5.

It is not appropriate for driving low impedance loads, since the voltage divider effect produced by the series and load resistors will reduce the signal amplitude at the load(s). Assuming you're using CMOS or FET loads, this will not be a problem, since the load resistance is high compared to the transmission line impedance. And, of course, since the load resistance is high, the power dissipated in the series resistor is also low.