I am trying to simulate a testbench on ModelSim, but when I run the simulation, it never advances in time. The delta does not increase, either.
Are there any useful tips for debugging in a situation like this? I suspect that the problem may not be in my testbench, but in the maze_solver
entity itself. Here are some possible problems:
maze_solver
also contains a structural description for another entity within it. Is it okay to simulate like this? As long as I have added that other entity into the ModelSim project?- Could it be a problem with my sensitivity lists? I have checked them all, and all the right-hand side signals have been included on the sensitivity lists.
- Could it be a problem with my testbench? I have included the testbench code below.
Since the maze_solver
design is long, I have not included it, but I can include it if necessary. It is a finite state machine (uses only case and if statements).
Below is my testbench:
library IEEE;
use IEEE.std_logic_1164.all;
entity solver_testbench is
end entity solver_testbench;
architecture tb of solver_testbench is
signal clk,reset: STD_LOGIC;
signal cell_data: STD_LOGIC_VECTOR (7 downto 0);
signal data_rdy: STD_LOGIC;
signal rd, wr: STD_LOGIC;
signal row, column: integer;
component maze_solver is
generic(maze_width : in integer);
Port (clk, reset : in STD_LOGIC;
start : in STD_LOGIC;
rd_cell_data : in STD_LOGIC_VECTOR (7 downto 0);
data_rdy: in STD_LOGIC;
rd,wr: out STD_LOGIC;
row, column: out integer
);
end component maze_solver;
begin
aravindans_maze_solver: maze_solver
generic map(maze_width=>2)
port map(clk=>clk, reset=>reset, start=>'1',rd_cell_data=>cell_data, data_rdy=>data_rdy, rd=>rd, wr=>wr,
row=>row, column=>column);
process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
process
begin
cell_data <= (others=>'0');
if rd = '1' then
if row = 0 and column = 0 then
cell_data <= "01000000";
data_rdy <= '1';
wait for 20 ns;
data_rdy <= '0';
elsif row = 0 and column = 1 then
cell_data <= "00010000";
data_rdy <= '1';
wait for 20 ns;
data_rdy <= '0';
elsif row = 1 and column = 0 then
cell_data <= "00000000";
data_rdy <= '1';
wait for 20 ns;
data_rdy <= '0';
elsif row = 1 and column = 1 then
cell_data <= "00000000";
data_rdy <= '1';
wait for 20 ns;
data_rdy <= '0';
end if;
else
cell_data <= (others => '0');
data_rdy <= '0';
end if;
end process;
reset <= '0', '1' after 5 ns;
end architecture tb;