Does anybody have a reference to an in depth explanation of hardware implementation of CORDIC algorithm for sine/cosine calculation? I'm looking for a way to model it in Verilog on structural level. I was able to do it on behavioral level, but when code got synthesized, I got way to many gates, so now I want to optimize the design by describing it structurally. I would appreciate any help.
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\$\begingroup\$ Working out this algorithm can be fun and very educational if at times frustrating project. I might suggest starting with a C program or similar modeling the calculation with relatively few bits until you understand how it works. If you just need a solution though, silicon vendor's tools may provide one as a configurable function. \$\endgroup\$– Chris StrattonCommented Dec 27, 2011 at 4:45
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\$\begingroup\$ I did the simulation in both C and Matlab -- it works. Coding is not a problem. I understand algorithm. Also this is a school project so I can't use ready made solution. Instead, I would like to understand better how real hardware would work. Some sites (like en.wikibooks.org/wiki/Digital_Circuits/CORDIC provide RTL schematic, but direct implementation doesn't work. I probably missing some small detail (probably on initialization stage), that's why I want to read something describing functioning of existing hardware and figure out what I'm doing wrong \$\endgroup\$– user6266Commented Dec 27, 2011 at 6:04
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\$\begingroup\$ Try to represent the algorithm in terms of shifts, additions, and conditional control logic. Also, try to keep the pipelining natural, ie, your output will be delayed from the input by the number of pipeline stages. \$\endgroup\$– Chris StrattonCommented Dec 27, 2011 at 13:03
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\$\begingroup\$ Ray Andraka wrote a very good survey on CORDIC implementations on FPGAs. Implementation of barrel shifters (or variable delays) can be costly, depending on platform, but dual port RAM blocks can do the trick with a clever addressing scheme. I have a good bitserial design for Altera's Cyclone IV (2 RAM blocks for 23 bit precision). \$\endgroup\$– AndreasCommented Nov 2, 2016 at 18:22
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As Chris suggested, the best would be to use a macro provided by the technology vendor. Otherwise, you would need to study alternative structures for implementing a CORDIC core.
From your description of having too many gates, you might just be using an architecture that is not suited for hardware implementation.
Your Verilog model needs to be based on hardware building blocks (RAM, multipliers, logic) instead of software algorithms. HDL synthesis tools do not magically convert algorithms to hardware blocks efficiently.
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\$\begingroup\$ Yes, as I said, I was using behavioral code and what I'm trying to do now is to use hardware building blocks, but I don't know how. \$\endgroup\$– user6266Commented Dec 27, 2011 at 6:01
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1\$\begingroup\$ In actuality the whole point of CORDIC is that it is an efficient algorithm for hardware implementation, without needing a "multiplier" - actually, you can multiply an input value by the calculated sin/cosine for free (except for a scaling, which you can generally move to a preceding or following stage), which is often what you want to be doing with the result anyway \$\endgroup\$ Commented Dec 27, 2011 at 13:08
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\$\begingroup\$ @user6266 - sit down and work through your algorithm and think in terms of hardware instead of software. It requires a paradigm shift in thinking - physically instead of virtually. Then, you should be able to figure out how e.g. if you need an array as a look-up-table, this could be implemented as a ROM, and write the code for a ROM. \$\endgroup\$– sybreonCommented Jan 4, 2012 at 7:18