Why am I getting ZZZ output for my Verilog cordic code?

Question

module Cordic_multiplier_16bit(Xin,Yin,Zin,clk,Xn,Yn,Zn); 
input [15:0]Xin,Yin,Zin;  
output reg [15:0]Xn = 16'b0,Yn= 16'b0,Zn= 16'b0; 
input clk; 
wire [15:0]X,Y,Z; 

//output variables for each stage  
wire[15:0]w1,w4,w7,w10,w13,w16,w19,w22,w25,w28,w31,w34,w37,w40,w43,w46; 
wire[15:0]w2,w5,w8,w11,w14,w17,w20,w23,w26,w29,w32,w35,w38,w41,w44,w47;
wire[15:0]w3,w6,w9,w12,w15,w18,w21,w24,w27,w30,w33,w36,w39,w42,w45,w48;

wire[15:0]R1,R4,R7,R10,R13,R16,R19,R22,R25,R28,R31,R34,R37,R40,R43,R46; 
wire[15:0]R2,R5,R8,R11,R14,R17,R20,R23,R26,R29,R32,R35,R38,R41,R44,R47;
wire[15:0]R3,R6,R9,R12,R15,R18,R21,R24,R27,R30,R33,R36,R39,R42,R45,R48;

 //LUT table 
reg [15:0]LUT1=16'b0001000110010011; 
reg [15:0]LUT2=16'b0000100000101100; 
reg [15:0]LUT3=16'b0000010000000100; 
reg [15:0]LUT4=16'b0000001000000000; 
reg [15:0]LUT5=16'b0000000100000000; 
reg [15:0]LUT6=16'b0000000010000000; 
reg [15:0]LUT7=16'b0000000001000000; 
reg [15:0]LUT8=16'b0000000000100000; 
reg [15:0]LUT9=16'b0000000000010000; 
reg [15:0]LUT10=16'b0000000000001000; 
reg [15:0]LUT11=16'b0000000000000100; 
reg [15:0]LUT12=16'b0000000000000010; 
reg [15:0]LUT13=16'b0000000000000001; 
reg [15:0]LUT14=16'b0000000000000001; 
 
reg_16bit REG01(X,Xin,clk); 
reg_16bit REG02(Y,Yin,clk);//storing Xin,Yin,Zin values in X,Y,Z  
reg_16bit REG03(Z,Zin,clk); 

//1st stage 
adder_sub_block ASB1(Y[15:0],X[15:0],~Y[15],w1); 
reg_16bit REG1(R1,w1,clk); 
adder_sub_block ASB2(Y[15:0],X[15:0],~Y[15],w2); 
reg_16bit REG2(R2,w2,clk); 
adder_sub_block ASB3(Z[15:0],LUT1,Y[15],w3); 
reg_16bit REG3(R3,w3,clk); 

//2nd stage 
adder_sub_block ASB4(R1,Y[15:0]>>>1,~R2[15],w4); 
reg_16bit REG4(R4,w4,clk); 
adder_sub_block ASB5(R2,X[15:0]>>>1,~R2[15],w5); 
reg_16bit REG5(R5,w5,clk); 
adder_sub_block ASB6(R3[15:0],LUT2,R2[15],w6); 
reg_16bit REG6(R6,w6,clk); 

//3rd stage 
adder_sub_block ASB7(R4,Y[15:0]>>>2,~R5[15],w7); 
reg_16bit REG7(R7,w7,clk); 
adder_sub_block ASB8(R5,X[15:0]>>>2,~R5[15],w8); 
reg_16bit REG8(R8,w8,clk); 
adder_sub_block ASB9(R6[15:0],LUT3,R5[15],w9); 
reg_16bit REG9(R9,w9,clk); 

//4th stage 
adder_sub_block ASB10(R7,Y[15:0]>>>3,~R8[15],w10); 
reg_16bit REG10(R10,w10,clk); 
adder_sub_block ASB11(R8,X[15:0]>>>3,~R8[15],w11); 
reg_16bit REG11(R11,w11,clk); 
adder_sub_block ASB12(R9[15:0],LUT4,R8[15],w12); 
reg_16bit REG12(R12,w12,clk); 

//5th stage 
adder_sub_block ASB13(R10,Y[15:0]>>>4,~R11[15],w13); 
reg_16bit REG13(R13,w13,clk); 
adder_sub_block ASB14(R14,X[15:0]>>>4,~R11[15],w14); 
reg_16bit REG14(R14,w14,clk); 
adder_sub_block ASB15(R15[15:0],LUT4,R11[15],w15); 
reg_16bit REG15(R15,w15,clk);

//6th stage 
adder_sub_block ASB16(R16,Y[15:0]>>>5,~R14[15],w16); 
reg_16bit REG16(R16,w16,clk); 
adder_sub_block ASB17(R17,X[15:0]>>>5,~R14[15],w17); 
reg_16bit REG17(R17,w17,clk); 
adder_sub_block ASB18(R18[15:0],LUT5,R11[15],w18); 
reg_16bit REG18(R18,w18,clk); 

//7th stage 
adder_sub_block ASB19(R19,Y[15:0]>>>6,~R17[15],w19); 
reg_16bit REG19(R19,w19,clk); 
adder_sub_block ASB20(R20,X[15:0]>>>6,~R17[15],w20); 
reg_16bit REG20(R20,w20,clk); 
adder_sub_block ASB21(R21[15:0],LUT6,R17[15],w21); 
reg_16bit REG21(R21,w21,clk); 

//8th stage 
adder_sub_block ASB22(R22,Y[15:0]>>>7,~R20[15],w22); 
reg_16bit REG22(R22,w22,clk); 
adder_sub_block ASB23(R23,X[15:0]>>>7,~R20[15],w23); 
reg_16bit REG23(R23,w23,clk); 
adder_sub_block ASB24(R24[15:0],LUT7,R20[15],w24); 
reg_16bit REG24(R24,w24,clk); 
 
//9th stage 
adder_sub_block ASB25(R25,Y[15:0]>>>8,~R23[15],w25); 
reg_16bit REG25(R25,w25,clk); 
adder_sub_block ASB26(R26,X[15:0]>>>8,~R23[15],w26); 
reg_16bit REG26(R26,w26,clk); 
adder_sub_block ASB27(R27[15:0],LUT8,R23[15],w27); 
reg_16bit REG27(R27,w27,clk); 

//10th stage 
adder_sub_block ASB28(R28,Y[15:0]>>>9,~R26[15],w28); 
reg_16bit REG28(R28,w28,clk); 
adder_sub_block ASB29(R29,X[15:0]>>>9,~R26[15],w29); 
reg_16bit REG29(R29,w29,clk); 
adder_sub_block ASB30(R30[15:0],LUT9,R26[15],w30); 
reg_16bit REG30(R30,w30,clk);

//11th stage 
adder_sub_block ASB31(R31,Y[15:0]>>>10,~R29[15],w31); 
reg_16bit REG31(R31,w31,clk); 
adder_sub_block ASB32(R32,X[15:0]>>>10,~R29[15],w32); 
reg_16bit REG32(R32,w32,clk); 
adder_sub_block ASB33(R33[15:0],LUT10,R29[15],w33); 
reg_16bit REG33(R33,w33,clk); 

//12th stage 
adder_sub_block ASB34(R34,Y[15:0]>>>11,~R32[15],w34); 
reg_16bit REG34(R34,w34,clk); 
adder_sub_block ASB35(R35,X[15:0]>>>11,~R32[15],w35); 
reg_16bit REG35(R35,w35,clk); 
adder_sub_block ASB36(R36[15:0],LUT11,R32[15],w36); 
reg_16bit REG36(R36,w36,clk);  

//13th stage 
adder_sub_block ASB37(R37,Y[15:0]>>>12,~R35[15],w37); 
reg_16bit REG37(R37,w37,clk); 
adder_sub_block ASB38(R38,X[15:0]>>>12,~R35[15],w38); 
reg_16bit REG38(R38,w38,clk); 
adder_sub_block ASB39(R39[15:0],LUT12,R35[15],w39); 
reg_16bit REG39(R39,w39,clk); 

//14th stage 
adder_sub_block ASB40(R40,Y[15:0]>>>13,~R38[15],w40); 
reg_16bit REG40(R40,w40,clk); 
adder_sub_block ASB41(R41,X[15:0]>>>13,~R38[15],w41); 
reg_16bit REG41(R41,w41,clk); 
adder_sub_block ASB42(R42[15:0],LUT13,R38[15],w42); 
reg_16bit REG42(R42,w42,clk);

//15th stage 
adder_sub_block ASB43(R43,Y[15:0]>>>14,~R41[15],w43); 
reg_16bit REG43(R43,w43,clk); 
adder_sub_block ASB44(R44,X[15:0]>>>14,~R41[15],w44); 
reg_16bit REG44(R44,w44,clk); 
adder_sub_block ASB45(R45[15:0],LUT13,R41[15],w45); 
reg_16bit REG45(R45,w45,clk); 

//16th stage 
adder_sub_block ASB46(R46,Y[15:0]>>>15,~R44[15],w46); 
reg_16bit REG46(R46,w46,clk); 
adder_sub_block ASB47(R47,X[15:0]>>>15,~R44[15],w47); 
reg_16bit REG47(R47,w47,clk); 
adder_sub_block ASB48(R48[15:0],LUT14,R44[15],w48); 
reg_16bit REG48(R48,w48,clk); 
endmodule 

//Pipeline Register 
module reg_16bit(out,in,clk); 
input clk; 
input [15:0]in; 
output reg [15:0]out; 
always@(posedge clk) 
begin 
out<=in; 
end 
endmodule 

module adder_sub_block(A,B,Cin,out); 
input [15:0]A,B; 
input Cin; 
output reg [15:0]out; 
always@(Cin) 
case(Cin) 
1:out=A-B; 
0:out=A+B; 
endcase 
endmodule



module stimulus;
reg [15:0] X, Y,Z;
wire [15:0] X_out, Y_out, Z_out;
reg clk;
initial
    $monitor($time, "X_out = %b, Y_out = %b, Z_out = %b",X_out, Y_out, Z_out);

  initial 
  begin 
    clk <= 1'b0;
    #2000 $finish;
  end

  always #30 clk = ~clk;
  
  initial 
  begin 
     X <= 33; Y <= 31; Z<=0;  
  end    
endmodule

here is the output for the above code:

0X_out = zzzzzzzzzzzzzzzz, Y_out = zzzzzzzzzzzzzzzz, Z_out = zzzzzzzzzzzzzzzz
main.v:199: $finish called at 2000 (1s)

Im Groot · Accepted Answer · 2024-03-15 09:20:51Z

You are getting Z at outputs because you have not instantiated your module Cordic_multiplier_16bit in the testbench stimulus. In your current stimulus, X_out, Y_out and Z_out are just a couple of wires that are not connected and are undriven and that is the root cause of Z.

You are generating the inputs in the testbench but you are not feeding those to your Cordic_multiplier_16bit in the testbench. Here is what you should do in the testbench:

module stimulus;
    reg [15:0] X, Y,Z;
    wire [15:0] X_out, Y_out, Z_out;
    reg clk;
    initial
        $monitor($time, "X_out = %b, Y_out = %b, Z_out = %b",X_out, Y_out, Z_out);

  initial 
  begin 
    clk <= 1'b0;
    #2000 $finish;
  end

  always #30 clk = ~clk;
  
  initial 
  begin 
     X <= 33; Y <= 31; Z<=0;  
  end    
  
  
  Cordic_multiplier_16bit DUT(
      .Xin(X),
      .Yin(Y),
      .Zin(Z),
      .clk(clk),
      .Xn(X_out),
      .Yn(Y_out),
      .Zn(Z_out)
  ); 
 
endmodule

toolic · Accepted Answer · 2024-03-15 09:24:08Z

You get z for your output because the signals that you monitored have no drivers.

You declared these signals as type wire in the stimulus module, and wires have the default value of z in Verilog (high impedance). You need to add an instance of the top-level design in the testbench module:

module stimulus;
reg  [15:0] X, Y, Z;
wire [15:0] X_out, Y_out, Z_out;
reg clk;

Cordic_multiplier_16bit dut (
    .Xin  (X),
    .Yin  (Y),
    .Zin  (Z),
    .clk  (clk),
    .Xn   (X_out),
    .Yn   (Y_out),
    .Zn   (Z_out)
);

initial begin 
    $monitor($time, " X_out = %b, Y_out = %b, Z_out = %b", X_out, Y_out, Z_out);
    clk = 0;
    X = 33;
    Y = 31;
    Z = 0;  
    #2000 $finish;
end

always #30 clk = ~clk;

endmodule

This is the new output, showing that the z values are now resolved to known values:

               0 X_out = 0000000000000000, Y_out = 0000000000000000, Z_out = 0000000000000000

I also combined the 3 initial blocks into one for simplicity. I added a space after $time in the $monitor statement for clarity.

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