I have read somewhere that the gate capacitance (Cgs, Cgd) of a MOSFET is calculated as below:
Strong inversion:
Cgs=(2/3)Cox.W.L + Cov
Non-saturated:
Cgs=Cgd=(1/2)Cox.W.L + Cov
where Cov is overlap capacitance.
Could anyone explain where the formulas come from?
Reading in the tea leaves here, I'd surmise that for the case of:
your equation 2)\$C_{gs}=C_{gd}=\frac{1}{2}C_{ox}WL + C_{ov}\$
They are taking the gate to channel capacitance and dividing equally between the S & D.
In the case of:
your equation 1)\$C_{gs}=\frac{2}{3}C_{ox}WL + C_{ov}\$
It looks like they are lumping the pinched off part of the channel which is attached to the source.
In your equation #2, while this is not strictly wrong, it is the wrong way to look at it. It would be best to think in terms of gate to channel.
In your equation #1, that might only hold true in one particular channel condition. Once the channel pinches off the drain doesn't under go massive capacitance changes.
I'd be suspicious.
From the book "Operation and modelling of the MOS transistor" by Yannis Tsividis (recommended reading !!) the following equations from section 8.3.2 (page 391 in the 2nd edition). For strong inversion:
$$ C_{gs} = C_{ox} \dfrac{2(1+2\eta)}{3(1+\eta)^2} $$
$$ C_{gd} = C_{ox} \dfrac{2(\eta^2 + 2\eta)}{3(1+\eta)^2} $$
\$ \eta = \$ degree of non-saturation. With \$ \eta = 1\$ at \$V_{ds}=0\$.
So in the case with the channel fully pinched off \$ \eta = 0\$. We get the case of your equation #1.
Your equations are approximations to the capacitance seen between G-D and G-S of a mosfet in different regions of operation and they are derived based on the physical characteristics of the mosfet. Keep in mind that the physical mosfet is a symmetric device. In the case of N-MOS, the terminal with a lower voltage is called the source (since it sources the charge carriers i.e electrons) and the terminal at the higher voltage is called the drain. Now taking as an approximation, the GATE-OXIDE-CHANNEL form a capacitor with capacitance \$C_g=C_{ox}\cdot W\cdot L\$, if you look at the channel at different regions of operation you can easily derive the approximations.
Cutoff region: There is no channel, so the gate capacitance is seen across G-B $$C_{gb}=C_{ox}\cdot W\cdot L+2C_{ov}$$ notice 2 overlap capacitances are seen
Linear/Triode region: A uniform channel is formed, isolating the Gate from Bulk, so we can approximate that the capacitance is evenly shared between the source and drain $$C_{gs}=C_{gd}=\frac 1 2 C_{ox}\cdot W\cdot L+C_{ov}$$ now 1 overlap capacitance for each terminal
Saturation region: The channel is triangular and pinched off at the drain we approximate that 2/3 of the capacitance is between gate and source and no capacitance between gate and drain $$C_{gd}=C_{ov}, C_{gs}=\frac 2 3 C_{ox}\cdot W\cdot L+C_{ov}$$ you could assume \$C_{gd}=0\$ to simplify your calculations.
Important Note that these are mere approximations to the actual capacitance and are only good for developing intuition and performing quick "back of the envelope" calculations for designers.
The factor of 2/3 comes from looking at the spatially-resolved gradual-channel model. There (at VDsat) the inversion-layer density varies as the square-root of the distance measured from the drain. Integrate the density to get the total charge and you get Q = 2/3 Cox W L Vgst. Cgs=dQ/dVg and you get the quoted result. Of course this is only as good as the gradual-channel (GC) approximation. If you swear by GC you'll believe it. If you swear at GC, you'll have other ideas. Tsividis's analysis appears to be completely based on Brew's charge-sheet model. This is still a GC model: the formulation implicitly relocates the drain to the classical pinch-off point, entirely distorting the electrostatics of the drain region.
This might help you out.
Reference:
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Boston, 2001
