linear delay model

Question

I was reading about linear delay model....d=gh +p where p is parasitic delay, g is locial effort anf f is electical effort. I came across synopsis design compiler model code (the code written in the photo) : In that they define terms as given in this table: What I dont understand is how g/cin is resistance. It says something like " effective resistance of gate increases with logical effort of the gate but decreases with gate size" how? Is there some intuitive thing going on here , that they have defined resistance of a gate? ( gate resistance is actually infinite )How does it decrease with gate size?

Also why in books is it written propogation delay of gate? why gate? It should be of whole circuit , right? like prop. delay of whole 2 input nand gate. Am I missing something here?

Answer 1

1/ Effective resistance of gate:

You should understand it is similar Rds (for easy understand).

Gate size increase (Width increase) --> Effective resistance of gate will be decrease, very simple.

2/ Relationship:

It's not mean effective resistance equal to g/Cin. It's mean that: $$R_{eff} \propto \frac{g}{C_{in}}$$

It is simply relative:

• Large gate: C_in large, R_eff small and logical effort of the gate (g) will be large. Please deep read the define of the logical effort of the gate. (R small --> current Ids large, logical effort g large.)

3/ Gate or circuit:

I think that gate is NAND, NOR, NOT, NMOS, PMOS.

In the follow section of the book, you will learn about the logical effort of the circuit. Circuit, it means many stages.

Hope it help you.