CMOS inverter delay

Question

Please tell me whether my thoughts on the question below is correct or not. How does the delay of a CMOS inverter decrease when we increase the supply voltage? What I thought was if we increase the Vdd from say, 1.8 to 1.9 volt, the output node will charge to 1.9 volt in the same time as it charged to 1.8 volt,because the time constant of the charging path is constant in both the cases. So the time taken to charge to 1.8V is less . Is this thought correct? But, if we do this ,it turns out that the discharging time will increase as the output node is discharging from 1.9 V to zero (earlier it was 1.8 to zero). Is This correct ? If not can you please explain this reduction in delay in terms of time constant.? Thank You

Answer 1

Logic gates get faster when the supply voltage increases. What you call the "time constant" of the charging path, isn't constant: it depends on supply voltage. If you think of it as an \$RC\$ circuit, the capacitance \$C\$ remains roughly constant, but \$R\$ decreases with supply voltage (remember that with increased \$V_{GS}\$ on a transistor, its resistance goes down), so \$RC\$ goes down.

A more accurate way to think of it is this: the voltage swing increases with supply voltage, so to maintain the same speed the charging current should also increase with supply voltage (remembering the capacitor equation, \$t=\frac{CV}{I}\$). However, for MOSFETs in saturation, the charging current increases roughly with the square of supply voltage (remembering the MOSFET equation, \$I_D=k(V_{GS}-V_{TH})^2\$). Thus, the time spent charging goes down.

This is true up to a point: once the transistors get small enough so that they no longer follow square-law behavior (because of velocity saturation), the logic gate speed no longer improves with increased supply voltage (because the charging current no longer scales with the square of \$V_{GS}\$, but instead scales linearly). Thus, for the latest process nodes, don't expect to improve speed by changing the supply voltage.