3bit Gray counter using D Flip Flops and logic gates

Question

I am studying a lesson about Logic Design and circuits. I have a question I can not find the answer. How can I design a 3-bit Gray counter using D flip flops? I know what the Gray code is, I know what a counter, logic gates and D flip flops do, but I do not have an idea on how to do it.

Answer 1

If you can use freely the logic gates, you can do this way:

1. Extract from the truth table the logic function that defines each bit of the next state from the previous state: \$ b_0(n) = f(b_0(n-1), b_1(n-1), b_2(n-1)) \$

2. Create the logic network that implement the 3 logic functions that you have found;

3. Now put it in a feedback from the output to the input of 3 D flip-flops, so then at each clock edge the state will be updated;

4. Reset the circuit to the 000 state.

If you really know logic gates, flip flops and counters, you can easily understand how this circuit works, and the rest is a breeze.

Answer 2

Designing a two-bit graycode counter with D flip flops is easy. Simply have feed the inverting output of flop #1 to the input of flop #2, and have the non-inverting output of flop #2 feed the input of flop #1.

An interesting way to go beyond two bits is to design an asynchronous circuit which takes in a quadrature input and produces a graycode output; that output will change whenever one of the bits on the quadrature input changes. The other bit can then be fed to the output along with the output of the upper portion.

This approach is interesting both from the point of view of requiring only two edge-triggered latches for an arbitrary counter length, and also from the standpoint of being able to have an arbitrary-length counter whose frequency is dependent only upon the ability of the initial stage to handle it. If one needs e.g. a 32-bit counter, one could cascade a two-bit counter into a two-bit counter (yielding 3 bits, the upper one of which will change at 1/8 of the input frequency) and then feed that into a 6-bit counter (yielding 8 bits total, the upper one of which will change at 1/1024 of the input frequency), and then feed that into a two cascaded 13-bit counters (for the 32-bit result). Unlike a conventional ripple counter which can only be meaningfully sampled when it's not counting, the cascaded gray-code counter may be sampled at any time--even if the delay in the upper stages exceeds the input signal period--provided one samples the inputs and outputs of each stage and does a little "post-processing" of the sampled signal. While one could not test the counter logic using shift-register based testing logic approaches, one could have a "test" register that would switch muxiplexers so that the upper counters sections would advance at the same speed as the lower ones.

If you want to have all bits of the counter operate synchronously, you should figure that the bottom bit should change whenever it doesn't match the xor of all the other bits, and otherwise each bit should change if the preceding bit is set and all other bits before it are clear.