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I'm trying to figure out with the most minimal part count how to convert an input of a digital IC to an edge-triggered input.

I am using the 82C55 IC and the input on it I want to make negative edge-triggered is the WR input. This is because I want to control both WR and the clock of an external latch (74HC574) with only one GPIO pin of a microcontroller.

I am able to pull this off by using a multivibrator (CD4538) and connecting the output of it to WR but the thing with that is I have to add a capacitor and resistor to create my own timing.

Is there a simpler way to convert a level-based input (where an output happens based on what level the input is at) to an edge-triggered input without introducing unnecessary long timings (which could happen with my multivibrator approach) and without using too many extra parts?

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  • \$\begingroup\$ It seems as you have to rethink what you are asking. If you stick with the idea that you want a level to become an edge then ask yourself what should happen of the level signal stays at its level forever. The real issue is when!! So I think what you really mean is that you have a slow signal that changes levels from 0->1 or 1->0 and you want to create a relatively narrow pulse when that edge has occurred. \$\endgroup\$ Commented Nov 25, 2016 at 19:50

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It seems as you have to rethink what you are asking. If you stick with the idea that you want a level to become an edge then ask yourself what should happen of the level signal stays at its level forever. The real issue is when!! So I think what you really mean is that you have a slow signal that changes levels from 0->1 or 1->0 and you want to create a relatively narrow pulse when that edge has occurred.

If you really want a level change to become a pulse there is a relatively straight forward way to do that with a couple of flip flops and a gate. Here is an example of a digital circuit that converts a low to high level change to a high going pulse. The clocking shown is 50MHz so the output pulse is 20 nsec. The below circuit also has two additional preceding flip flops to delay the generated strobe by two clock times from the input edge. (Note that this design was taken from an FPGA implementation).

enter image description here

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