Problem in overflow detection in signed 2's complement 3-bit numbers

Question

According to this page, and other similar ones, the rules for detecting overflow when adding signed binary numbers in 2's complement form are the following:

• If the sum of two positive numbers yields a negative result, the sum has overflowed.
• If the sum of two negative numbers yields a positive result, the sum has overflowed.
• Otherwise, the sum has not overflowed.

This, however, appears not to work for 3-bit signed numbers. For example consider adding -2 and -2, +2 is 010 and it's 2's complement is then 110. Then -2+-2 = 110+110 = 1100. When we discard the carry, the sign of the number is negative, because -4 can not be represented as a 3-bit signed number. I am trying to optimize a design for a school assignment and currently the best I can do is just handle the case where it gets to 100 (I just turn the overflow flag on if this happens). Any help is much appreciated.

Answer 1

I did not go to the website to read the text of the rules you listed, but I think there is a semantic error somewhere. First, your assertion that -4 cannot be represented in 2-s complement is incorrect. The range of 3 bit 2's complement numbers is indeed -4 (100)... 3 (011). Second, the detection of overflow is based on extending the carry bit. For adding numbers with the same sign, as long as the extra/ MSB carry bit is the same as the original MSB, an overflow has not occurred....For example

-2 (110) -2 (110) -4 (1100) No overflow

-2 (110) -3 (101) -5 (1011) overflow

Answer 2

I think your premise is wrong, just do the addition like so and throw away the carry out (which by itself is actually the overflow detection in logic terms).

  | 1 1 0 = -2
+ | 1 1 0 = -2
------------
1 | 1 0 0 = -4