I read this sentence from a book: "MR is a dc reset". It said about master reset leg in a counter IC.
I have been searching but found nothing related to this terminology. I wonder what a dc reset is?
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3\$\begingroup\$ it means that the logic level (voltage level) activates the reset circuitry ... the reset stays active as long as the logic level is applied ....... the other type of reset would be an edge triggered reset .... the reset would happen at the transition of the logic level .... the reset would not remain active after the transition \$\endgroup\$– jsotolaCommented May 7, 2018 at 17:15
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3 Answers
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Without any context in your question other than "a book" the best that can be said is that it refers to the counter reset input on a digital counter chip. A defined logic 1 or 0 on this pin will reset the counter to a predefined count value - almost always zero.
The DC (capitals?) refers to direct current. This is a bit confusing as DC gives the impression that the voltage is constant whereas for the reset signal it will typically be a pulse. Again, without context, the best that can be said is that the author intends to convey the impression that the signal is DC coupled as in standard electronic logic.
answered May 7, 2018 at 12:54
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\$\begingroup\$ I'm sorry. It is in "Digital system" of Ronald Tocci. They are actually written in lower case letters, as "dc". \$\endgroup\$– W.JoeCommented May 7, 2018 at 12:56
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\$\begingroup\$ 'dc' could be 'da counter', or more likely, 'digital counter', in that context \$\endgroup\$– WillCommented May 7, 2018 at 13:18
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4\$\begingroup\$ Could be a different way of saying asynchronous or level-sensitive reset. The other type of reset is a synchronous reset, which happens only on a clock edge. \$\endgroup\$– crj11Commented May 7, 2018 at 13:24
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\$\begingroup\$ I think @crj11 is correct. OP should post the exact context or a scan of the surrounding text. \$\endgroup\$ Commented May 7, 2018 at 13:42
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I will assume that the reset operates on a high input here. If it's low to reset, just reverse high and low in the description below.
A reset signal could be edge-triggered, or not. If it's edge triggered, then the reset will happen when the MR goes from low to high, but then it will come out of reset, even if MR remains high.
By specifying that it's DC reset, then the system will reset when the MR pin goes from low to high, and remain reset until that pin goes low again.
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My WAG: Likely, since it is a IC, this is a "power-on reset", which conceptually, in ICs, is a reset that places all registered logic (that has a reset attached) to a known value. The fact that the author refers to it as "dc reset" is probably a pedantic detail he uses to make it clear that the reset is(/should be) sourced from the DC portion of whatever CCA/PCB the IC is instantiated upon.
