Merging multiple audio inputs into one audio output

Question

I am working on audio preamplifier project using Altium Designer, which is also a great opportunity to learn this particular piece of software. Now, I've selected Hierarchical design to be able to get benefits of Multi-Sheet and Multi-Channel Design:

Now, I have 8 audio relays, implemented with Repeat(AUDIO_INPUT_RELAY,1,8) command:

and here is Audio Input Relay Schematic itself:

Now, these 8 audio input relays converge into single SELECTED_AUDIO_OUTPUT_LEFT and single SELECTED_AUDIO_OUTPUT_RIGHT lines and here is whole subsheet:

I am aware a volume control is missing (the project is not finished), however, this is not topic now and my question is: when I compile this project, why do I get following error (I am aware I can disable error reporting in Project Options, which is also not the point here, I want to know what did I wrong):

Net SELECTED_AUDIO_OUTPUT_LEFT contains multiple Output Sheet Entrys (Sheet Entry AUDIO_INPUT_RELAY1-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY2-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY3-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY4-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY5-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY6-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY7-SELECTED_AUDIO_OUTPUT_LEFT(Output),Sheet Entry AUDIO_INPUT_RELAY8-SELECTED_AUDIO_OUTPUT_LEFT(Output))

and screenshot of error:

I have no unmatched ports and sheet entries, as @Radiohead gave a hint:

Answer 1

I think the problem might be that those ports, since they do not share a common name, Altium is unable to bind them together (even though you did so by using a wire).

This should fix it:

Design -> Synchronize Sheet Entries and Ports

There you'll have a menu with the available ports and sheet entries and you can assign them to each other, compile and everything should be fine.

EDIT

So, I've tried on Altium 16 to do a project more or less like yours.

First, I tried with two joined modules, with different entry and exit port names.

And I get a few warning because of that, but the project compiles

Then, when I assign the same name to entry and exit ports it compiles successfully (no warnings)

Try assigning the same name to the ports and compile again, see if it helps

Answer 2

For Altium, an Output Port asserts a signal the net. Logically, a net cannot be asserted different values by different sources,which makes it undefined. Altium cannot guess impedances of the ports,so unlesa you know what you do, it will assume this logical error.

I would get another sheet that "adds" the signals up and outputs the "sum"

I am writing this from the app, couldn't check you schematics honestly. Will do in 5 mins.

All right. This is not different from connecting output of 8 different ports to the same net, and then to an input port. I think the root cause is the fact that you are effectively connecting 8 different ports to one port. Altium doesn't know, of course whether this is sensible or not. We generally don't "add signals up" without an impedance or a resistance is in place.

You can do several things. One is to put a NoERC directive on the Net, it you are absolutely sure that the way that is interpreted right.

You can create a sheet that has 8 input ports that execute the adding functionality.