I have been working on an application which must read
I've come up with 2 potential solutions:
I'm aware that the implementation using a MCU would be way harder. What are potential problems in both methods.
Which solution looks better in your opinion?
You need 6.4 Million samples per second. Various companies produce 12-bit ADCs to handle that rate.
I designed a 12-bit 4-channel system, for 24MegaSample/sec total, decades ago. We burned about 8 watts total. Gain per channel was 1/2/4/8. You want UNITY gain, so that saves power what with no gain being needed, and only one channel.
We used 8-layer PCB; the deterministic noise was below the 11-bit level. The random noise density was about 15 nanoVolts/rtHertz. In 4MHz bandwidth, that produces 30 microVolts rms, or about 185 microVolts PP (6.2 sigma, 6.2RMS).
You want 12 bits in 3.3v, or about 800 microVolts per Vquanta. But 1% accuracy: offset error, gain error, non-linearity. We used auto-zero of offset and of gain, about every 1 minute.
To handle 12 bits (9 nepers of settling) in 160 nanoseconds, you need precise timing of the ADC StartConvert event, so you can guarantee about 100 nanoseconds for settling. That means you need the MUX and the Buffer and the ADC input RC filter to produce 100nanosec / 9 nepers == 11 nanoseconds of ONE_POLE settling. 11*6.28 = 70, inverted to be 14 MHz F3dB for the entire signal Chain.
At high-frequencies, analog Muxes have LOTS OF CROSSTALK, and lots of charge injection from the on-silicon turn-those-MUX_FET-gates on/off very quickly.That means the 32 signal sources must be able to quickly recover from injected charge (remember that 11-nanosecond time constant, and 100nS settling time budget), or else you must BUFFER each of the 32 inputs with an OpAmp able to quickly settle.
Here is the idea
The stage#4, the RC LPF, is the SLOWEST stage by far, thus a clean settling channel-switching response can be expected, despite MUX charge injection; in the lower left corner, you'll see the far-out phase is 90 degrees, indicating a clean 1-pole rolloff. The opamps are MCP655, unity gain, with settling Taus of about 4 nanoseconds. The ADC has 500 ohms Rin and 5picoFarad Sample, thus 2.5 nanosecond sample-hold timeconstant; the ADC switch charge injection will vary depending on which ADC you pick. The combined RC LPF and its driving opamp must handle ADC charge injection.
Look at the topright numbers: the tool predicts 11.3 bits.
You have to handle offset and gain and non-linearity of the ADC and opamps.
======== now consider the interference from a nearby switching power supply ====
If you have such a supply 1cm away, switching 0.1 amp in 10 nanoseconds, the coupling being into a trace in the signal chain path, the tool predicts the ENOB will fall to 6.5 bits (7 milliVolts RMS induced error, using wire-to-loop coupling). This is NOT inductor-flux-leakage modeling.
That RC filter, at 14MHz, has little effect on SwitchReg frequencies. You need to keep any Digital VDD traces at least an inch away from the Opamps and MUX and ADC input, and keep that Digital VDD trace OVER a plane, so the net magnetic flux is greatly constricted to remain mostly very near and under the VDD trace
Analog Devices makes an 8 & 16-channel simultaneusly sampled ADCs with 12 and more bits, but the results are still read out one channel at a time. Use their filtering to pick one and use 2, 3, 4 of them.
I've come up with 2 potential solutions
A ADG732 can only be part of the solution, because it's just a multiplexer ;-) There's no 12 bit ADC in it.
The STM32 has four independent ADCs and the datasheet specifies a min. total conversion time of 0.21µS - sounds great, but there are two issues:
This MCU has a max. clock of 72MHz. I doubt that it's possible to process 9.6MB/s in time or transmit it safely to somewhere else.
As the maximum total conversion time 8.52µs is specified, what would surely be a showstopper. The actual time is somewhere between min and max.
You will have to look for a different solution.
