Parasitic insensitive switched capacitor circuit

Question

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here:

I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using non-overlapping clocks with period 1us and pulse width 0.4 us. Both caps are 1pF. The schematic is shown below:

The opamp is generated using a vcvs with open-loop gain 1e20.

However, the output of my integrator seems to have a huge unexpected gain, instead of the predicted gain of 1. (Check out the swing in the next image). It also has some strange offset.

Does anyone know where I am going wrong with my simulation? Thanks.

Answer 1

The gain of the integrator is related to the clock frequency. Notice, \$K \approx C_1/(C_2T_{clk})\$ . (see David Johns, Ken Martin, 1st ed. 403).

I put together a simulation in LTspice. The concept should be the same in Cadence. Notice with a fixed input frequency, as the sampling clock frequency gets higher and higher relative to the fixed input signal frequency, the relative clock period is getting smaller and the gain is getting larger, as the equation predicts.

Also, using a vcvs allows for the gain to grow without boundaries (it would saturate to rails with more realistic amplifier). Two possible ways to adjust this are lower the oversampling ratio, and or adjust capacitance ratio. Also, the vcvs output can't swing below 0 like the input without additional offset applied (like subtraction).

edit. Didn't notice this was two years old, but it's a useful concept for anyone learning about switched capacitor integrators. And not obvious.

Answer 2

Some things to try:

To solve the offset problem try putting a large resistor to ground on the input of the VCVS, like 1e12 or larger. That way the simulation can find the DC operating point on startup.

To solve the gain issue, use an actual integrator with resistors
Source:https://www.electronics-tutorials.ws/opamp/opamp_6.html