can we do one always inside another always for verilog?

Question

I am wondering if the following statement could be supported by verilog. Basically I would like to be inside the posedge clock detection, in some cases to trigger a negedge detection as well. Is it doable?

I basically want to generate a divider (both even number and odd number). For example, for divider number of 10, I would only count the positive edge to generate a 50/50 duty cycle clock. in this case, only the positive clock edge detection is fine.

However, for divider number of 11, I would like to count the negative colck edge as well in order to generate a 50/50 duty cycle. So inside the positive clock edge detection, I would like to have a negative clock edge detection as well.

Can the negative clock edge detection be placed inside the positive clock edge detection loop?

  Always @(posedge clk) begin
     if (n=10) begin      
     always @(nededge clk) begin
          n=5;
          end
     end
     else 
     xxx
     end
endmodule

Answer 1

No, you can not.

what you can do is drop the 'always' and just wait for a negative clock edge:

 always @(posedge clk) 
 begin
    if (n==10) 
    begin      
       @(negedge clk) 
       begin
           n <= 5;
       end
     end
 end

Please realise that the code can only be used in a test-bench. You can not synthesize this.

---

Even for your code which removes always, it is still not synthesizable?

Nope! That is what I wrote. There is no single logic element that responds to both rising and falling clock edges.

All double edge logic like DDR interfaces are comprised of two sets of FFs: falling and rising edge and the results are combined. Most often transferring the falling edge data to the risign edge so you end up with double width data.

_{I had to fix your if (n=10) and nededge I suggest you be more careful even when making examples.}