I have some RFSoc Evaluation Kit with 12-bit DACs and ADCs that support nearly 4 GSPS
I found out that sampling rate is related to bandwidth.
From experiment, I found out that this board's DAC and ADC center frequency upper limit is about 1 GHz.
I wonder what factor would affect the upper bound of the DAC and ADC center frequency.
I used to doing research on signal processing and is new to electric. Can someone please help me or provide some idea. Thanks in advance.