Calculation of the capacitor value across the base and emitter to avoid unexpected turn ON of transistor

Question

There is a design recommendation to add a capacitor across the base and emitter of Q2 to avoid the unwanted/unexpected turn ON of Q2.

Calculation of new capacitor across Vbe:

My questions :

1. Can someone show me the current path and the voltage across the components when there is no capacitor across Vbe which will provide the unexpected turn ON of Q2 during high dV/dt at VBAT?

Please also show the current path and voltage across the components when there is capacitor added between base and emitter which will avoid the unexpected turn ON of Q2 during High dV/dt at VBAT?

Question 2 :

I am not able to understand the formula and how there are arriving at the value of the new capacitor which is taken to be 1nF. Can someone provide clear explanation of the formula?

If you cannot provide any answer related to the above circuit image and formula present in the question, I request you to provide your own simple circuit image explaining the current path and voltages in it with and without the base emitter capacitance and your formula for arriving at the base emitter capacitor value.

EDIT : In the above circuit image, the resistor R57 is 47k and 100mW (power rated) package. and R403 is 10k and 100mW (power package). There is no capacitor added across the base-emitter of the transistor. But there is a design recommendation for this circuit which recommends to add a capacitor across the base emitter of the transistor to avoid unexpected turn ON of the transistor during high dV/dt.

So, the formula attached above in the circuit asks to add a capacitor between the base emitter of the PNP transistor of a value of 1nF to avoid the unexpected turn ON of the transistor.

My question is, I just want to understand how the transistor turns ON during High dV/dt when there's NO capacitor across B-E junction of Q2 and when there's a capacitor of 1nF (which is recommended to add - coming based on the above formula) added to the base-emitter junction of Q2. Would like to know how the current flows and voltages across the components during both instances (with 1nF added and without 1nF)

Also, not sure what is the formula which is used above to arrive at 1nF. So, want to ask whether anyone has seen this type of formula to calculate the capacitor across B-E of the transistor. If you have not used this type of formulas, then how to arrive at the capacitor value.

Answer 1

The current path at Turn-ON. The capacitor is a short circuit.

And the current path with the additional capacitor across \$R_{57}\$ resistor with a much larger capacitance value then \$C_{CB0} + C_{LEAK}\$

Now the BJT won't be able to Turn ON because \$C_1 >> C_{CB0} + C_{LEAK}\$ and we have a capacitive voltage divider thus \$V_{BE} = V_{bat} \times \frac{C_{CB0}}{C_{CB0} + C_1} \approx 24V \times \frac{6pF}{1nF} \approx 0.114V \$ (at the end of a charing phase).

And after this \$C_1\$ capacitor will be discharged by \$R_{57}\$ resistor. So that the steady-state voltage at the base is equal to \$24V\$.

And at the same time, the small charging current will be flowing through \$ C_{CB0} + C_{LEAK}\$

Answer 2

From reading the question, and the operating condition of high dV/dT of collector_base voltage, you seek to understand the value of a capacitive voltage divider.

Ok

With rapid dV/dT across the Cap_ColBase (1.5pF, for example), the charging current needs to be absorbed somewhere, and NOT flow into the base_emitter region of the transistor.

I'd plan to add a large enough cap across emitter_base to hold the delta_V_BE to less than 0.1 volts, or perhaps even 0.05 volts.

Assume 1.5pF needs to be charged as the collector voltage quickly changes by 24 volts, and we want to hold the base_emitter voltage change to 0.05 volts, the ratio is

• 24volts / 0.05 volts = 24 * 20 = 480X.

Thus we should consider adding 1.5 pF * 480 == 480 + 240 = 720 pF.

For design margin, use at least 1,000 pF.

=========================

Another way is to actively clamp the base_emitter voltage to near zero.

This requires a low R_out driver.

If the 24 volts transitions in 24 nanoSeconds, the peak current is

• I = C * dV/dT = 1.5pF * 24volt/24nS = 1.5e-12 * 1e+9 volts per second.

or

• I = 1.5 milliAmps

And we need to hold the change in base_emitter voltage to less than 0.05 volts

Thus the output resistance (incremental resistance) of the base_driver circuit needs to be less than

• R_incremental = V / I = 0.05v / 1.5mA = 0.05 / 0.0015 = 5/0.15 = 35 ohms

And you need a design (safety) margin, to be provided under ALL conditions.

I'd plan on 10 ohms, or less.