0
\$\begingroup\$

schematic

simulate this circuit – Schematic created using CircuitLab


Int the above schematic I tried to calculate the what the end product would be.
So I considered Input as A and Output as B. 
. is and, + is or and ' is not
(A.B)'= B
=> A' + B' = B

Here if B is 1, A has to be 0
but if B is 0 then B' becomes 1 making the equation nonsensical
(Is there a reason why the simulation is showing 0?)

\$\endgroup\$
6
  • \$\begingroup\$ Is this a digital simulation or an analog simulation aware of the actual construction of the gates? \$\endgroup\$
    – nanofarad
    Commented Sep 2, 2021 at 14:47
  • \$\begingroup\$ It's a digital simulation. I just want to see how to breakdown this logic \$\endgroup\$
    – Saphereye
    Commented Sep 2, 2021 at 14:49
  • \$\begingroup\$ A digital simulation cannot accommodate this behavior because it is not well-described using digital principles alone. Depending on the exact analog behavior of both gates, you've built either an inverting amplifier in feedback with enable, or a ring oscillator with enable, or some other pathological behavior. \$\endgroup\$
    – nanofarad
    Commented Sep 2, 2021 at 14:53
  • \$\begingroup\$ But you have made an oscillator (generator). \$\endgroup\$
    – G36
    Commented Sep 2, 2021 at 14:54
  • \$\begingroup\$ you are right, but what you are not taking into account is the timely behavior of the model. in your design, think of A as an enable signal, since if A is 0, output is always high but if it's 1, lets say output initially is 0, after the time it takes for the signal to go thorough AND and inverter, output then becomes 1, and then 0, and 1 again, and so on \$\endgroup\$
    – NeuroEng
    Commented Sep 2, 2021 at 14:59

1 Answer 1

Reset to default
0
\$\begingroup\$

What you have is a gated oscillator: the output will feed back the input, which changes the output state (after a time), and it does this over and over until the other AND input is brought low. This is a useful circuit for some purposes (like PLLs or clock generators) but as a logic element it doesn’t make sense.

Digital simulators will show this behavior if they model gate delays, with the frequency being determined by the gate unit delays. An analog sim will show this oscillation (try it in Falstad for example.)

This oscillation comes up with a circuit commonly referred to as a ‘JK flip flop’ that is actually a JK latch: when both J and K inputs are high, it oscillates when the ‘clock’ (actually enable) is high. More about this here: JK latch, possible Ben Eater error?

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.